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    Operating voltage selection circuit for non-volatile semiconductor memories
    4.
    发明公开
    Operating voltage selection circuit for non-volatile semiconductor memories 失效
    电路，用于选择的非易失性半导体存储器的操作电压

    公开(公告)号：EP1498905A3

    公开(公告)日：2006-12-13

    申请号：EP04023387.6

    申请日：1998-02-26

    Applicant: STMicroelectronics S.r.l.

    Inventor： Rolandi, Paolo

    IPC: G11C16/00 ,  G11C16/06 ,  G11C5/14 ,  G11C7/00

    CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C7/1045 ,  G11C16/20 ,  G11C2207/2227

    Abstract: An operating voltage selection circuit for non-volatile semiconductor memories, whose particularity resides in the fact that it comprises:
    -- means (1) for reading at least one one-time programmable non-volatile memory cell (10), suitable to generate a signal (LV) which indicates the requested type of operating voltage of a non-volatile memory, which depends on the programmed or non-programmed state of the memory cell;
    -- memory enabling means (5), which comprise an inverter (30, 31) and are provided with means (32) for modifying the switching threshold of the inverter as a function of the signal that indicates the requested type of operating voltage;
    -- output means (2), which are connected to means for sensing data of the memory and to output terminals of the memory, comprising a CMOS inverter (20, 50) and means (23) for modifying the output current of the inverter as a function of the signal (LV) for indicating the requested type of operating voltage; and
    -- means (8) for the internal synchronization of the memory, which comprise pluralities of transistors (40, 41, 42) connected in a series/parallel configuration which is determined by the signal (LV) for indicating the requested type of operating voltage, in order to generate signals (CK1, CK2, CK3) for the internal synchronization of the memory.

    Reference cells matrix structure for reading data in a nonvolatile memory device
    9.
    发明公开
    Reference cells matrix structure for reading data in a nonvolatile memory device 有权
    Referenzzellenmatrixanordnung zum Datenlesen在einernichtflüchtigenSpeicheranordnung

    公开(公告)号：EP1160795A1

    公开(公告)日：2001-12-05

    申请号：EP00830393.5

    申请日：2000-05-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Rolandi, Paolo ,  Montanaro, Massimo ,  Oddone, Giorgio

    IPC: G11C16/28 ,  G11C11/56

    CPC classification number: G11C16/28 ,  G11C11/5621 ,  G11C11/5642 ,  G11C2211/5634

    Abstract: The invention relates to a circuit structure (1) for reading data contained in an electrically programmable/erasable integrated non-volatile memory device, comprising a matrix (2) of memory cells (3) and at least one reference cell (4) for comparison with a memory cell (3) during a reading phase. The reference cell (4) is incorporated in a reference cells sub-matrix (5) which is structurally independent of the matrix (2) of memory cells (3).
    Also provided is a conduction path between the matrix (2) and the sub-matrix (5), which path includes bit lines (b1ref) of the submatrix (5) of reference cells (4) extended continuously into the matrix (2) of memory cells (3)

    Abstract translation: 本发明涉及一种用于读取包含在电可编程/可擦除的集成非易失性存储器件中的数据的电路结构（1），其包括存储器单元（3）的矩阵（2）和用于比较的至少一个参考单元（4） 在读取阶段期间具有存储器单元（3）。 参考单元（4）被并入参考单元子矩阵（5）中，其在结构上独立于存储单元（3）的矩阵（2）。 还提供了矩阵（2）和子矩阵（5）之间的传导路径，该路径包括连续延伸到矩阵（2）中的参考单元（4）的子矩阵（5）的位线（b1ref） 存储单元（3）

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