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    Voltage boosting device
    1.
    发明公开
    Voltage boosting device 有权
    Spannungserhöhungsvorrichtung

    公开(公告)号：EP1124313A1

    公开(公告)日：2001-08-16

    申请号：EP00830088.1

    申请日：2000-02-08

    Applicant: STMicroelectronics S.r.l.

    Inventor： Rolandi, Paolo ,  Montanaro, Massimo ,  Oddone, Giorgio

    IPC: H02M3/07

    CPC classification number: H02M3/07

    Abstract: A voltage boosting device for speeding power-up of multilevel nonvolatile memories, including a voltage regulator (11) and a charge pump (13) and having an output terminal (10); the voltage regulator (11) having a regulation terminal connected to the output terminal (10), and an output (16) supplying a control voltage (V L ); the read charge pump (13) having an output connected to the output terminal (10) and supplying a read voltage (V R ). The device further includes an enable circuit (12) connected to the output (16) and having a pump enable output (17) connected to a charge pump enable terminal (13) and supplying a pump enable signal (PE). The pump enable signal (PE) is set at a first logic level so as to activate the charge pump (13) when the read voltage (V R ) is lower than a nominal value. In addition, the device generates a power-up sync signal (ATDS) which activates a read operation when the read voltage (V R ) reaches its nominal value and a chip enable signal (CE) is set at an active value.

    Abstract translation: 一种用于加速包括电压调节器（11）和电荷泵（13）并具有输出端子（10）的多电平非易失性存储器的上电的升压装置; 具有连接到输出端子（10）的调节端子的调压器（11）和提供控制电压（VL）的输出端（16）; 所述读取电荷泵（13）具有连接到所述输出端子（10）并提供读取电压（VR）的输出。 该装置还包括连接到输出端（16）并且具有连接到电荷泵使能端子（13）并提供泵使能信号（PE）的泵使能输出（17）的使能电路（12）。 泵使能信号（PE）被设置在第一逻辑电平，以便当读取电压（VR）低于额定值时激活电荷泵（13）。 此外，器件产生上电同步信号（ATDS），当上述读取电压（VR）达到其标称值且芯片使能信号（CE）被设置为有效值时，该同步信号激活读取操作。

    Reference cells matrix structure for reading data in a nonvolatile memory device
    5.
    发明公开
    Reference cells matrix structure for reading data in a nonvolatile memory device 有权
    Referenzzellenmatrixanordnung zum Datenlesen在einernichtflüchtigenSpeicheranordnung

    公开(公告)号：EP1160795A1

    公开(公告)日：2001-12-05

    申请号：EP00830393.5

    申请日：2000-05-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Rolandi, Paolo ,  Montanaro, Massimo ,  Oddone, Giorgio

    IPC: G11C16/28 ,  G11C11/56

    CPC classification number: G11C16/28 ,  G11C11/5621 ,  G11C11/5642 ,  G11C2211/5634

    Abstract: The invention relates to a circuit structure (1) for reading data contained in an electrically programmable/erasable integrated non-volatile memory device, comprising a matrix (2) of memory cells (3) and at least one reference cell (4) for comparison with a memory cell (3) during a reading phase. The reference cell (4) is incorporated in a reference cells sub-matrix (5) which is structurally independent of the matrix (2) of memory cells (3).
    Also provided is a conduction path between the matrix (2) and the sub-matrix (5), which path includes bit lines (b1ref) of the submatrix (5) of reference cells (4) extended continuously into the matrix (2) of memory cells (3)

    Abstract translation: 本发明涉及一种用于读取包含在电可编程/可擦除的集成非易失性存储器件中的数据的电路结构（1），其包括存储器单元（3）的矩阵（2）和用于比较的至少一个参考单元（4） 在读取阶段期间具有存储器单元（3）。 参考单元（4）被并入参考单元子矩阵（5）中，其在结构上独立于存储单元（3）的矩阵（2）。 还提供了矩阵（2）和子矩阵（5）之间的传导路径，该路径包括连续延伸到矩阵（2）中的参考单元（4）的子矩阵（5）的位线（b1ref） 存储单元（3）

    Reading circuit and method for a multilevel non volatile memory
    9.
    发明公开
    Reading circuit and method for a multilevel non volatile memory 有权
    Leseschaltkreis undzugehörigesVerfahrenfürnichtflüchtigenMehrpegel-Speicher

    公开(公告)号：EP1249841A1

    公开(公告)日：2002-10-16

    申请号：EP01830248.9

    申请日：2001-04-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pagliato, Mauro ,  Rolandi, Paolo ,  Montanaro, Massimo

    IPC: G11C11/56

    CPC classification number: G11C11/5642 ,  G11C11/56 ,  G11C11/5621 ,  G11C2211/5632

    Abstract: Described herein is an asynchronous serial dichotomic sense amplifier (10) comprising a first comparator stage (12) having a first input receiving the cell current (I CELL ) flowing in the multilevel memory cell (18), the content of which is to be read, a second input receiving a first reference current (I REF2 ), and an output supplying the first of the bits stored in the multilevel memory cell (18); a multiplexer stage (16) having a selection input (16c) connected to the output of the first comparator stage (12), a first signal input (16a) receiving a second reference current (I REF1 ), a second signal input (16b) receiving a third reference current (I REF3 ), and a signal output (16d) selectively connectable to the first or the second signal input (16a, 16b) depending on the logic level present on the selection input (16c); and a second comparator stage (14) having a first input receiving the cell current (I CELL ), a second input connected to the signal output (16d) of the multiplexer stage (16), and an output supplying the second of the bits stored in the multilevel memory cell (18).

    Abstract translation: 读取电路包括异步串行二色读取器（12,14,16）。 读取器包括比较器（12）。 比较器的输出提供存储在多电平存储单元（18）中的一个位。 选择器（16）具有连接到比较器的输出和两个信号输入的选择输入。 选择器具有可选择性地连接到两个信号输入之一的输出，这取决于选择输入上的逻辑电平。 电路还包括第二比较器（14）。 还包括以下独立权利要求：（a）多层存储单元的读取方法。

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