公开(公告)号：WO2011079879A1

公开(公告)日：2011-07-07

申请号：PCT/EP2010/005926

申请日：2010-09-29

Applicant: STMICROELECTRONICS S.R.L. ,  BOTTAREL, Valeria ,  RICOTTI, Giulio ,  MARABELLI, Silvia

Inventor： BOTTAREL, Valeria ,  RICOTTI, Giulio ,  MARABELLI, Silvia

IPC: H03K17/693 ,  H03K17/74 ,  H03K17/687 ,  H03K17/06 ,  B06B1/02 ,  H03K17/0812 ,  H03K17/0814

CPC classification number: H03K17/693 ,  B06B1/0215 ,  H03K17/06 ,  H03K17/08122 ,  H03K17/08142 ,  H03K17/6872 ,  H03K17/74

Abstract: A low voltage isolation circuit (1) is described inserted between an input terminal (HVout) suitable for receiving a high voltage signal (IM) and an output terminal (pzt) suitable for transmitting the high voltage signal (IM) to a load (PZ) of the type comprising at least one driving block (5) inserted between a first and a second voltage reference (Vss, -Vss) and comprising a first driving transistor (Ml), inserted between the first voltage reference (Vss) and a first driving central circuit node (Xc) and a second driving transistor (M2), in turn inserted between the driving central circuit node (Xc) and the second supply voltage reference (-Vss) as well as an isolation block (8) connected to the connection terminal (pzt), to the input terminal (HVout) and, through a protection block (9) comprising a first and a second protection transistor (MD1, MD2), being in anti-series to each other and having control terminals receiving respective complementary protection driving signals (dr1, dr2), to the driving central circuit node (Xc), the isolation block (8) comprising at least one voltage limiter block (6), a diode block (7) and a control transistor (MD), in turn connected across the diode block (7) between the input (HVout) and output (pzt) terminals of the low voltage isolation switch (1) and having a control terminal (XD) connected to the driving central circuit node (Xc) through the protection block (9), said diode block (7) comprising at least one first and one second transmission diode (DN1, DN2), connected in antiparallel, i.e. by having an anode terminal of said first diode connected to a cathode terminal of said second diode and vice versa.

Abstract translation: 描述了一种低压隔离电路（1），其插入适于接收高电压信号（IM）的输入端（HVout）和适于将高电压信号（IM）发送到负载（PZ）的输出端（pzt）之间 ）包括插入在第一和第二电压参考（Vss，-Vss）之间的至少一个驱动块（5），并且包括插入在第一电压参考（Vss）和第一电压参考（Vss）之间的第一驱动晶体管（M1） 驱动中心电路节点（Xc）和第二驱动晶体管（M2），其又插入在驱动中心电路节点（Xc）和第二电源电压参考（-Vss）之间，以及隔离块（8） 连接端子（pzt）到输入端子（HVout），并且通过包括第一和第二保护晶体管（MD1，MD2）的保护块（9）彼此反串联并且具有相应的控制端子 互补保护驾驶信号（dr1，dr 如图2所示，驱动中心电路节点（Xc），隔离块（8）包括至少一个限压器块（6），二极管块（7）和控制晶体管（MD） 在低压隔离开关（1）的输入（HVout）端子和输出端子（pzt）端子之间具有通过保护块（9）连接到驱动中心电路节点（Xc）的控制端子（XD）的块（7） ，所述二极管块（7）包括至少一个反并联连接的第一和第二传输二极管（DN1，DN2），即通过使所述第一二极管的阳极端子连接到所述第二二极管的阴极端子，反之亦然。

公开(公告)号：WO2011045083A1

公开(公告)日：2011-04-21

申请号：PCT/EP2010/006339

申请日：2010-10-18

Applicant: STMICROELECTRONICS S.R.L. ,  RICOTTI, Giulio ,  BOMPIERI, Paolo ,  ROSSI, Sandro

Inventor： RICOTTI, Giulio ,  BOMPIERI, Paolo ,  ROSSI, Sandro

IPC: H03K17/74

CPC classification number: H03K17/063

Abstract: The invention relates to a High Voltage switch configuration (10) having an input terminal (IN) which receives an input signal (Vin) to drive a load and an output terminal (OUT) which issues an output signal (Vout) to the load. Advantageously according to the invention, the High Voltage switch configuration ( 10) comprises at least a first and a second diode (D1, D2), being placed in antiseries between said input and output terminals (IN, OUT) and having a pair of corresponding terminals in common, in correspondence of a first internal circuit node (Xc1).

Abstract translation: 本发明涉及一种具有接收输入信号（Vin）以驱动负载的输入端（IN）和向负载发出输出信号（Vout）的输出端（OUT）的高压开关配置（10）。 有利地，根据本发明，高压开关配置（10）至少包括第一和第二二极管（D1，D2），放置在所述输入和输出端子（IN，OUT）之间的反电容中，并具有一对相应的 端子，对应于第一内部电路节点（Xc1）。

公开(公告)号：WO2007010570A1

公开(公告)日：2007-01-25

申请号：PCT/IT2005/000431

申请日：2005-07-22

Applicant: STMICROELECTRONICS S.R.L. ,  RICOTTI, Giulio ,  MORELLI, Marco ,  DELLA TORRE, Luigi ,  VITALI, Andrea, Lorenzo ,  MASTROMATTEO, Ubaldo

Inventor： RICOTTI, Giulio ,  MORELLI, Marco ,  DELLA TORRE, Luigi ,  VITALI, Andrea, Lorenzo ,  MASTROMATTEO, Ubaldo

IPC: G01L9/06 ,  G01L19/06

CPC classification number: G01L9/0054 ,  G01L9/0045 ,  G01L15/00

Abstract: In a pressure sensor (15) with double measuring scale: a monolithic body (16) of semiconductor material has a first main surface (16a), a bulk region (17) and a sensitive portion (33) upon which pressure (P) acts; a cavity (18) is formed in the monolithic body (16) and is separated from the first main surface (16a) by a membrane (19), which is flexible and deformable as a function of the pressure (P), and is arranged inside the sensitive portion (33) and is surrounded by the bulk region (17); a low-pressure detecting element (28) of the piezoresistive type, sensitive to first values of pressure (P), is integrated in the membrane (19) and has a variable resistance as a function of the deformation of the membrane (19); in addition, a high-pressure detecting element (29), also of a piezoresistive type, is formed in the bulk region (17) inside the sensitive portion (33) and has a variable resistance as a function of the pressure (P). The high­pressure detecting element (29) is sensitive to second values of pressure (P).

Abstract translation: 在具有双重测量标尺的压力传感器（15）中：半导体材料的整体（16）具有第一主表面（16a），主体区域（17）和压力（P）作用于其上的敏感部分 ; 在整体式主体（16）中形成空腔（18），并且通过膜（19）与第一主表面（16a）分离，该膜（19）作为压力（P）的函数是柔性和可变形的，并且布置 在所述敏感部分（33）的内部并且被所述主体区域（17）包围; 对第一压力值（P）敏感的压阻型低压检测元件（28）集成在膜（19）中，并具有作为膜（19）的变形的函数的可变电阻; 此外，在敏感部分（33）内的主体区域（17）中形成压阻型高压检测元件（29），并具有作为压力（P）的函数的可变电阻。 高压检测元件（29）对第二压力值（P）敏感。

公开(公告)号：EP4258544A1

公开(公告)日：2023-10-11

申请号：EP23166296.6

申请日：2023-04-03

Applicant: Alma Mater Studiorum Universita di Bologna ,  STMicroelectronics S.r.l.

Inventor： ELGANI, Alessia Maria ,  D'ADDATO, Matteo ,  PERILLI, Luca ,  FRANCHI SCARSELLI, Eleonora ,  GNUDI, Antonio ,  CANEGALLO, Roberto Antonio ,  RICOTTI, Giulio

IPC: H03D1/18

Abstract: An envelope detector (50) having an envelope extracting portion (51) and a temperature compensating portion (52). The envelope extracting portion (51) has a first extraction transistor (13) and a second extraction transistor (14) coupled at an intermediate node (17). The first extraction transistor (13) has a first current conduction terminal coupled to a first connection node (16); a second current conduction terminal coupled to the intermediate node (17); and a control terminal coupled to the signal input node (23) and to a biasing node (24). The second extraction transistor (14) has a first current conduction terminal coupled to the intermediate node (17); a second current conduction terminal coupled to a second connection node (19); and a control terminal coupled to the biasing node (24). The temperature compensating portion (52) has a first temperature compensating transistor (58) that is diode-connected and coupled between a compensation output node (65) and the second connection node (19). The second connection node (19) is coupled to the compensation output node (65) and the first connection node (16) is coupled to a detector output (21).

公开(公告)号：EP3185415B1

公开(公告)日：2018-07-25

申请号：EP16172129.5

申请日：2016-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： SAUTTO, Marco ,  QUAGLIA, Fabio ,  RICOTTI, Giulio ,  MAZZANTI, Andrea

IPC: H03F3/00 ,  H03F3/45 ,  H03F3/217 ,  H03G1/00

CPC classification number: H03G1/0094 ,  H03F3/005 ,  H03F3/2175 ,  H03F3/45 ,  H03F3/45264 ,  H03F2200/312 ,  H03F2203/45288

Abstract: In an embodiment, a programmable-gain amplifier includes: two complementary cross-coupled transistor (e.g. MOS) pairs (M n-a , M n-b ; M p-a , M p-b ) mutually coupled with each transistor in one pair (M n-a resp. M n-b ) having a current flow path cascaded with a current flow path of a respective one of the transistors in the other pair (M p-a resp. M p-b ) to provide first (A) and second (B) coupling points between said complementary cross-coupled transistor pairs (M n-a , M n-b ; M p-a , M p-b ); first (C a ) and second (C b ) sampling capacitors set between the first (A) and second (B) coupling points, respectively, and ground; first (10) and second (12) input stages having input terminals for receiving input signals (V in- , V in+ ) for sampling by the first (C a ) and second (C b ) sampling capacitors. Switching means (201 to 206; 301, 302) are provided for: - i) coupling the first (10) and second (12) input stages to the first (C a ) and second (C b ) sampling capacitors, whereby the input signals (V in- , V in+ ) are sampled as sampled signals (V out+ , V out- ) on said first (C a ) and second (C b ) sampling capacitors, and - ii) energizing (V dd ) the complementary cross-coupled transistor pairs (M n-a , M n-b ; M p-a , M p-b ) whereby the signals (V out+ , V out- ) sampled on the first (C a ) and second (C b ) sampling capacitors undergo negative resistance regeneration growing exponentially over time, thereby providing an exponential amplifier gain.

公开(公告)号：EP3185415A1

公开(公告)日：2017-06-28

申请号：EP16172129.5

申请日：2016-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： SAUTTO, Marco ,  QUAGLIA, Fabio ,  RICOTTI, Giulio ,  MAZZANTI, Andrea

IPC: H03F3/00 ,  H03F3/45

CPC classification number: H03G1/0094 ,  H03F3/005 ,  H03F3/2175 ,  H03F3/45 ,  H03F3/45264 ,  H03F2200/312 ,  H03F2203/45288

Abstract: In an embodiment, a programmable-gain amplifier includes: two complementary cross-coupled transistor (e.g. MOS) pairs (M n-a , M n-b ; M p-a , M p-b ) mutually coupled with each transistor in one pair (M n-a resp. M n-b ) having a current flow path cascaded with a current flow path of a respective one of the transistors in the other pair (M p-a resp. M p-b ) to provide first (A) and second (B) coupling points between said complementary cross-coupled transistor pairs (M n-a , M n-b ; M p-a , M p-b ); first (C a ) and second (C b ) sampling capacitors set between the first (A) and second (B) coupling points, respectively, and ground; first (10) and second (12) input stages having input terminals for receiving input signals (V in- , V in+ ) for sampling by the first (C a ) and second (C b ) sampling capacitors. Switching means (201 to 206; 301, 302) are provided for:
- i) coupling the first (10) and second (12) input stages to the first (C a ) and second (C b ) sampling capacitors, whereby the input signals (V in- , V in+ ) are sampled as sampled signals (V out+ , V out- ) on said first (C a ) and second (C b ) sampling capacitors, and
- ii) energizing (V dd ) the complementary cross-coupled transistor pairs (M n-a , M n-b ; M p-a , M p-b ) whereby the signals (V out+ , V out- ) sampled on the first (C a ) and second (C b ) sampling capacitors undergo negative resistance regeneration growing exponentially over time, thereby providing an exponential amplifier gain.

Abstract translation: 在一个实施例中，可编程增益放大器包括：与一对中的每个晶体管（Mn-a，Mn-b; Mp-a， （Mp-a或Mp-b）中的相应一个晶体管的电流流动路径级联的电流流动路径以提供第一（A）和第二（B） 所述互补交叉耦合晶体管对（Mn-a，Mn-b; Mp-a，Mp-b）之间的耦合点; 分别在第一（A）和第二（B）耦合点之间设置的第一（Ca）和第二（Cb）采样电容器以及地; 第一（10）和第二（12）输入级具有用于接收输入信号（Vin-，Vin +）以供第一（Ca）和第二（Cb）采样电容器采样的输入端。 提供切换装置（201至206; 301,302）用于：i）将第一（10）和第二（12）输入级耦合至第一（Ca）和第二（Cb）采样电容器，由此输入信号 Vin和Vin +）在所述第一（Ca）和第二（Cb）采样电容器上被采样为采样信号（Vout +，Vout-），以及-ii）激励（Vdd）互补交叉耦合晶体管对（Mn- 由此在第一（Ca）和第二（Cb）采样电容器上采样的信号（Vout +，Vout-）经历随时间呈指数增长的负电阻再生，由此提供指数放大器增益 。

公开(公告)号：EP2132868A1

公开(公告)日：2009-12-16

申请号：EP07736756.3

申请日：2007-04-03

Applicant: STMicroelectronics S.r.l.

Inventor： MURARI, Bruno ,  MASTROMATTEO, Ubaldo ,  RICOTTI, Giulio

IPC: H02N1/00

CPC classification number: H02N1/006

Abstract: An electrostatic micromotor (10') is provided with a fixed substrate (12), a mobile substrate (13) facing the fixed substrate (12), and electrostatic-interaction elements (14, 15, 17) enabling a relative movement of the mobile substrate (3) with respect to the fixed substrate (2) in a movement direction (x); the electrostatic micromotor is also provided with a capacitive position-sensing structure (18') configured to enable sensing of a relative position of the mobile substrate (13) with respect to the fixed substrate (12) in the movement direction (x). The capacitive position-sensing structure (18') is formed by at least one sensing indentation (22), extending within the mobile substrate (13) from a first surface (13a; 13b) thereof, and by at least one first sensing electrode (24), facing, in at least one given operating condition, the sensing indentation (22).

公开(公告)号：EP2656502A1

公开(公告)日：2013-10-30

申请号：EP10818066.2

申请日：2010-12-23

Applicant: STMicroelectronics S.r.l.

Inventor： BOTTAREL, Valeria ,  RICOTTI, Giulio ,  QUAGLIA, Fabio

IPC: H03K17/081 ,  H03K17/30 ,  G01S7/52 ,  B06B1/02

CPC classification number: H03K17/16 ,  H03K17/08104 ,  H03K17/30

Abstract: A low voltage isolation switch is suitable for receiving from a connection node a high voltage signal and transmitting said high voltage signal to a load via a connection terminal. The isolation switch includes a driving block connected between first and second voltage reference terminals and including a first driving transistor coupled between the first voltage reference (Vss) and a first driving circuit node and a second driving transistor coupled between the driving circuit node and the second supply voltage reference. The switch comprises an isolation block connected to the connection terminal (pzt), the connection node, and the driving central circuit node and including a voltage limiter block, a diode block and a control transistor. The control transistor is connected across the diode block between the connection node and the connection terminal and has a control terminal connected to the driving central circuit node.

公开(公告)号：EP2489126A1

公开(公告)日：2012-08-22

申请号：EP10776932.5

申请日：2010-10-18

Applicant: STMicroelectronics S.r.l.

Inventor： RICOTTI, Giulio ,  BOMPIERI, Paolo ,  ROSSI, Sandro

IPC: H03K17/74

CPC classification number: H03K17/063

Abstract: The invention relates to a High Voltage switch configuration (10) having an input terminal (IN) which receives an input signal (Vin) to drive a load and an output terminal (OUT) which issues an output signal (Vout) to the load. Advantageously according to the invention, the High Voltage switch configuration ( 10) comprises at least a first and a second diode (D1, D2), being placed in antiseries between said input and output terminals (IN, OUT) and having a pair of corresponding terminals in common, in correspondence of a first internal circuit node (Xc1).

公开(公告)号：EP1938068A1

公开(公告)日：2008-07-02

申请号：EP05802413.4

申请日：2005-09-16

Applicant: STMicroelectronics S.r.l.

Inventor： MURARI, Bruno ,  RICOTTI, Giulio ,  DELLA TORRE, Luigi ,  VITALI, Andrea, Lorenzo

IPC: G01L1/02 ,  G01L9/00

CPC classification number: G01L9/0054 ,  G01L1/02 ,  G01L5/225 ,  G01L9/0045 ,  G01L9/0089 ,  G01L19/0645 ,  G01L19/146

Abstract: In a pressure sensor (35), a pressure-sensor element (10) has a monolithic body (12) of semiconductor material, and a first main face (12a) and a second main face (12b) acting on which is a stress resulting from a pressure (P) the value of which is to be determined; and a package (36) encloses the pressure-sensor element (10). The package (36) has an inner chamber (37) containing liquid material (38), and the pressure-sensor element (10) is arranged within the inner chamber (37) in such a manner that the first and second main faces (12a, 12b) are both in contact with the liquid material (38). In particular, the liquid material is a silicone gel.