公开(公告)号：EP2061152A1

公开(公告)日：2009-05-20

申请号：EP08105569.1

申请日：2004-05-05

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco

IPC: H03M1/00

CPC classification number: G11C27/026 ,  G11C27/024 ,  H03H19/004 ,  H03K5/2481 ,  H03K5/249 ,  H03M1/0682 ,  H03M1/468

Abstract: A switched capacitance circuit including:
- a switched capacitance section (SC), capable of receiving as input a signal (V IMP , V IMM ) and carrying out a sampling of said signal, the section comprising at least one group (AR, AR') of capacitors (Ca, Cb, Cc, Ca', Cb', Cc') each of which has a terminal connected to a common node (NS, NS');
- at least an operational stage (CMP) including at least an input terminal (IN, IN') connected to said common node (NS, NS'), the operational stage (CMP) providing a current to said common node (NS, NS') for charging said group (AR, AR') of capacitors during a sampling time interval of said signal (V INP , V INM ).
The circuit further includes an auxiliary circuit (ANC) connected to said common node (NS, NS') and capable of being activated/deactivated by an enabling signal (PRECH) for injecting a further current into said common node (NS, NS') and increasing the current provided to said common node (NS, NS') during at least one time interval equal to a fraction of said sampling interval.

Abstract translation: 一种开关电容电路，包括： - 一个开关电容部分（SC），能够接收作为输入的信号（V IMP，V IMM）和进行所述信号的一个取样的，所述部分包括至少一组（AR，AR' ）电容器（CA，CB，抄送钙 'CB'，Cc的 '（），其中每个具有连接到公共节点NS，NS终端'）; - 至少在包括操作阶段（CMP）至少到输入端子“连接到所述公共节点（NS，NS），运算步骤（CMP）提供电流到所述公共节点（NS，NS（IN，IN）” “），用于充电所述组（AR，AR”，所述信号（V INP，V INM）的采样时间间隔期间电容）。 该电路还包括连接到所述公共节点（NS，NS“）辅助电路（ANC）上（并能够被激活/通过在使能信号（PRECH）用于注入另一电流到所述公共节点NS，NS）去激活” 并且在至少一个时间间隔等于所述取样间隔的分数增加提供给所述公共节点（NS，NS“）的电流。

公开(公告)号：EP1566888B1

公开(公告)日：2007-05-23

申请号：EP04425100.7

申请日：2004-02-18

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco ,  Nagari, Angelo

IPC: H03K3/03

CPC classification number: H03K3/0315 ,  H03K3/03 ,  H03K5/133 ,  H03K2005/00071

公开(公告)号：EP1583244A1

公开(公告)日：2005-10-05

申请号：EP04425241.9

申请日：2004-04-01

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco ,  Girardi, Francesca

IPC: H03M1/46

CPC classification number: H03M1/002 ,  H03M1/462

Abstract: The described converter comprises switched-capacitor quantization means (DAC, COMP) for receiving an analog quantity to be converted (VIN), a register (REG) for a digital quantity corresponding to the analog quantity, a timing pulse generator (CLK-GEN) and logic means (LOG) capable of responding to a conversion request signal (CONVREQ) by activating the quantization means in such a way that they will carry out predetermined operations timed by the timing pulses and load in the register (REG) the digital quantity to be furnished as output (OUTBUS). With a view to saving electric energy during the conversion and reducing the noise induced by the generator, the generator (CLK-GEN) comprises means for modifying the duration and/or the frequency of the timing pulses in response to regulation signals (REGBUS0, REGBUS1) emitted by the logic means.
Also described is a method of using the converter that comprises the following phases: loading of the analog quantity (VIN) in the quantization means (DAC, COMP), memorization of the loaded analog quantity and identification in the course of successive attempts in accordance with SAR technique of the bits of the digital code corresponding to the analog quantity to be converted. The duration and/or the frequency of the timing pulses are modified during at least one of the phases indicated above in response to regulation signals emitted by the logic means (LOG).

公开(公告)号：EP1566888A1

公开(公告)日：2005-08-24

申请号：EP04425100.7

申请日：2004-02-18

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco ,  Nagari, Angelo

IPC: H03K3/03

CPC classification number: H03K3/0315 ,  H03K3/03 ,  H03K5/133 ,  H03K2005/00071

Abstract: The circuit comprises a first ring oscillator (OSC1) comprising an odd number of inverting elements, a delay element (DA) and an output terminal (N); the delay element (DA) responds to a pulse at its input (IN-DA) with a predetermined time delay (d(DA)) with respect to a predetermined edge of the input pulse and substantially without time delay with respect to the other edge of the input pulse. With a view to avoiding start-up transients and generating pulses with a duty cycle that can be easily modified, the circuit comprises a second ring oscillator (OSC2) equal to the first, having an output terminal connected to the output terminal (N) of the first oscillator, and a bistable logic circuit having an output terminal connected to the common output (N) of the first and the second oscillator. At least one of the inverting elements of the first oscillator (OSC1) and at least one of the inverting elements of the second oscillator (OSC2) form part of the bistable logic circuit.

Abstract translation: 该电路包括包括奇数个反相元件的第一环形振荡器（OSC1），延迟元件（DA）和输出端子（N）; 延迟元件（DA）相对于输入脉冲的预定边缘以预定的时间延迟（d（DA））在其输入端（IN-DA）处响应脉冲，并且相对于另一边缘基本上没有时间延迟 的输入脉冲。 为了避免启动瞬变并产生可以容易地修改的占空比的脉冲，该电路包括等于第一环路振荡器（OSC2）的第二环形振荡器（OSC2），其具有连接到输出端子（N）的输出端子 第一振荡器和双稳态逻辑电路，其输出端连接到第一和第二振荡器的公共输出端（N）。 第一振荡器（OSC1）的反相元件和第二振荡器（OSC2）的反相元件中的至少一个的至少一个形成双稳态逻辑电路的一部分。