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    Process for manufacturing an array of cells including selection bipolar junction transistors
    12.
    发明公开
    Process for manufacturing an array of cells including selection bipolar junction transistors 有权
    用于与所述选择晶体管的双极电池装置和相关联的小区布置的制造方法

    公开(公告)号：EP1408549A1

    公开(公告)日：2004-04-14

    申请号：EP02425604.2

    申请日：2002-10-08

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Pellizzer, Fabio ,  Casagrande, Guilio ,  Gastaldi, Roberto ,  Vendrame, Loris ,  Benvenuti, Augusto ,  Lowrey, Tyler, c/o Ovonyx Inc.

    IPC: H01L27/10 ,  H01L29/68 ,  H01L45/00

    CPC classification number: H01L29/685 ,  H01L27/101 ,  H01L27/24

    Abstract: A process for manufacturing an array of cells, including: implanting, in a body (10) of semiconductor material of a first conductivity type, a common conduction region (11) of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions (12) of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer (21) having first and second openings (27a, 27b); implanting first portions of the active area regions through the first openings (27a) with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions (14) of the first conductivity type; implanting second portions of the active area regions through the second openings (27b) with a doping agent of the second conductivity type, thereby forming control contact regions (15) of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components (3), each storage component having a terminal connected to a respective second conduction region (14).

    Abstract translation: 单元的阵列是通过注入第一导电类型，以通过绝缘层的第一开口有源区区域的第一部分的掺杂剂，以形成第二导电区制成; 注入第二导电类型到穿过绝缘层以形成控制接触区域的第二开口的有源区域的区域的第二部分中的掺杂剂; 和在所述主体的顶部上形成存储元件。 单元阵列的制造包括：提供第一导电类型的半导体材料的本体（10）; 植入在身体中，第一导电类型的公共导电区（11）; 形成在所述主体中，公共导电区域上方，有源区的区域的第二导电类型和第一掺杂水平的（12）; 形成，在所述主体的顶部，绝缘层上具有第一和第二开口（27A，27B）; 通过用第一导电类型的掺杂剂的第一开口注入所述有源区区域的第一部分，从而形成在所述有源区区域中的第一导电类型的第二传导区域; 通过注入与所述第二导电类型的掺杂剂的第二孔中的活性区域的区域的第二部分，所述第二导电类型和第二掺杂水平比所述第一掺杂等级高的形成，从而控制接触区域（15）; 并形成存储元件（24）在所述主体的顶部上。 每个控制接触区域形成，与所述第二传导区域和公共传导区，选择双极型晶体管（20）连接在一起。 每个存储组件具有连接到第二respectivement传导区的端子。 它定义，与双极晶体管，所述单元阵列的细胞一起。

    A content addressable memory cell
    16.
    发明公开
    A content addressable memory cell 有权
    关于可选内容存储单元

    公开(公告)号：EP1526547A1

    公开(公告)日：2005-04-27

    申请号：EP03103898.7

    申请日：2003-10-22

    Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

    Inventor： De Sandre, Guido ,  Bez, Roberto ,  Pellizzer, Fabio

    IPC: G11C15/04

    CPC classification number: G11C15/04 ,  G11C13/0004 ,  G11C14/00 ,  G11C14/009 ,  G11C15/046

    Abstract: A content addressable memory cell (105) for a non-volatile Content Addressable Memory (100), including non-volatile storage means (S1,S2,S) for storing a content digit, a selection input (WL i ;WL i ,BLP j ) for selecting the memory cell, a search input for receiving a search digit (BLR j ,BLL j ), and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output (ML i ) of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage means include at least one Phase-Change Memory element (S1,S2,S) for storing in a non-volatile way the respective content digit.

    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step
    17.
    发明公开
    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step 有权
    一种用于制造存储器件，特别是相变存储器，具有硅化方法

    公开(公告)号：EP1439579A1

    公开(公告)日：2004-07-21

    申请号：EP03425017.5

    申请日：2003-01-15

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Pellizzer, Fabio ,  Bez, Roberto ,  Tosi, Marina

    IPC: H01L21/8234 ,  H01L21/8239

    CPC classification number: H01L21/823835 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: A process wherein an insulating region (13) is formed in a body at least around an array portion (51) of a semiconductor body (10); a gate region (16) of semiconductor material is formed on top of a circuitry portion (51) of the semiconductor body (10); a first silicide protection mask (52) is formed on top of the array portion; the gate region (16) and the active areas (43) of the circuitry portion (51) are silicided and the first silicide protection mask (52) is removed. The first silicide protection mask (52) is of polysilicon and is formed simultaneously with the gate region (16). A second silicide protection mask (53) of dielectric material covering the first silicide protection mask (52) is formed before silicidation of the gate region (16). The second silicide protection mask (53) is formed simultaneously with spacers (41) formed laterally to the gate region (16).

    Abstract translation: 的方法worin到绝缘区域（13）在一个主体中形成至少围绕到一半导体主体的阵列部分（51）（10）; 半导体材料的栅极区（16）形成在所述半导体主体的一个电路部分（51）的顶部（10）; 的第一硅化物保护掩模（52）是形成在阵列部分的顶部上; 栅极区（16）和所述电路部（51）的有源区（43）被硅化并且所述第一硅化物保护掩模（52）被去除。 第一硅化物保护掩模（52）是多晶硅，并且与所述栅极区域（16）同时形成。 覆盖所述第一硅化物保护掩模（52）的介电材料的第二硅化物保护掩模（53）的栅极区（16）的硅化之前形成。 第二硅化物保护掩模（53）与形成尾盘反弹到栅极区域（16）间隔件（41）同时形成。

    Array of cells including a selection bipolar transistor and fabrication method thereof
    18.
    发明公开
    Array of cells including a selection bipolar transistor and fabrication method thereof 有权
    Zellenanordnung mit Bipolar-Auswahl-Transistor和Herstellungsverfahren

    公开(公告)号：EP1408550A1

    公开(公告)日：2004-04-14

    申请号：EP02425605.9

    申请日：2002-10-08

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Pellizzer, Fabio ,  Casagrande, Giulio ,  Bez, Roberto

    IPC: H01L27/10 ,  H01L29/68 ,  H01L45/00

    CPC classification number: H01L27/2445 ,  H01L27/101 ,  H01L27/2463 ,  H01L29/685 ,  H01L45/06 ,  H01L45/1233

    Abstract: A cell array (1) is formed by a plurality of cells (2) including each a selection bipolar transistor (4) and a storage component (3). The cell array is formed in a body (10) including a common collector region (11) of P type; a plurality of base regions (12) of N type, overlying the common collector region (11); a plurality of emitter regions (14) of P type formed in the base regions; and a plurality of base contact regions (15) of N type and a higher doping level than the base regions, formed in the base regions (12; 42), wherein each base region (12) is shared by at least two adjacent bipolar transistors (20).

    Abstract translation: 电池阵列包括设置在主体（10）中的P型公共集电极区域（11）上的N型基极区域（12）的数量。 在基极区域中形成P型发射极区域（14）和N型基极接触区域（15），使得基极接触区域的掺杂水平高于基极区域的掺杂水平，并且每个基极区域由 至少两个双极晶体管（20）。 电池阵列制造过程中还包括独立权利要求。

    Phase change memory cell and manufacturing method thereof using minitrenches
    19.
    发明公开
    Phase change memory cell and manufacturing method thereof using minitrenches 有权
    相变存储单元，并且借助于minitrenches及其制造方法

    公开(公告)号：EP1339110A9

    公开(公告)日：2004-01-28

    申请号：EP02425087.0

    申请日：2002-02-20

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Bez, Roberto ,  Pellizzer, Fabio ,  Tosi, Marina ,  Zonca, Romina

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: The phase change memory cell (5) is formed by a resistive element (22) and by a memory region (38) of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction (Y) ; and the memory region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) transverse to the first dimension. The first thin portion (22) and the second thin portion (38a) are in direct electrical contact and define a contact area (58) of sublithographic extension. The second thin portion (38a) is delimited laterally by oxide spacer portions (55a) surrounded by a mold layer (49) which defines a lithographic opening (51). The spacer portions (55a) are formed after forming the lithographic opening, by a spacer formation technique.

    Contact structure, phase change memory cell, and manufacturing method thereof with elimination of double contacts
    20.
    发明公开
    Contact structure, phase change memory cell, and manufacturing method thereof with elimination of double contacts 有权
    Kontaktstruktur，Phasenwechsel-Speicherzelle und deren Herstellungsverfahren mit Elimination von Doppelkontakten

    公开(公告)号：EP1339111A1

    公开(公告)日：2003-08-27

    申请号：EP02425089.6

    申请日：2002-02-20

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Pellizzer, Fabio

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: G11C11/5678 ,  G11C11/56 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: The phase change memory cell (5) is formed by a resistive element (22) and by a memory region (38) of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction (Y); and the memory region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) which is transverse to said first direction. The first and second thin portions (22, 38a) are in direct electrical contact and define a contact area (58) having sublithographic extent. The second thin portion (38a) is formed in a slit of sublithograhic dimensions. According to a first solution, oxide spacer portions (55a) are formed in a lithographic opening (51), delimited by a mold layer (49). According to a different solution, a sacrificial region is formed on top of a mold layer and is used for forming the sublithographic slit in the mold layer.

    Abstract translation: 相变存储单元（5）由电阻元件（22）和相变材料的存储区域（38）形成。 电阻元件具有在第一方向（Y）上具有第一亚光刻尺寸的第一薄部分。 并且所述存储区域（38）具有在横向于所述第一方向的第二方向（X）上具有第二亚光刻尺寸的第二薄部分（38a）。 第一和第二薄部分（22,38a）处于直接电接触并且限定具有亚光刻范围的接触区域（58）。 第二薄部分（38a）形成在亚光刻尺寸的狭缝中。 根据第一解决方案，氧化物隔离部分（55a）形成在由模具层（49）限定的光刻开口（51）中。 根据不同的解决方案，牺牲区形成在模具层的顶部上，并用于在模具层中形成亚光刻缝。

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