公开(公告)号：US20230141173A1

公开(公告)日：2023-05-11

申请号：US17983856

申请日：2022-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Hagyoul BAE ,  Jinseong HEO

IPC: H01L29/78 ,  H01L27/118 ,  H01L29/49 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/78391 ,  H01L27/11807 ,  H01L29/4908 ,  H01L29/42392 ,  H01L29/78645 ,  H01L29/78696 ,  H01L2027/11838

Abstract: According to various example embodiments, a semiconductor element includes: a channel layer including a semiconductor material; a p-type semiconductor layer and an n-type semiconductor layer apart from each other with the channel layer therebetween, a paraelectric layer on a first area of the channel layer, a ferroelectric layer on a second area different from the first area of the channel area, and having a polarization state due to a voltage applied from an external source, a first gate electrode on the paraelectric layer, a second gate electrode on the ferroelectric layer, and an insulating layer between the first gate electrode and the second gate electrode, and electrically separating the first gate electrode and the second gate electrode from each other.

公开(公告)号：US20220173255A1

公开(公告)日：2022-06-02

申请号：US17461034

申请日：2021-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Taehwan MOON ,  Hagyoul BAE ,  Seunggeol NAM ,  Sangwook KIM ,  Kwanghee LEE

IPC: H01L29/86 ,  H01L27/115 ,  H01L51/05 ,  H01L27/28

Abstract: A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

公开(公告)号：US20230186086A1

公开(公告)日：2023-06-15

申请号：US18063936

申请日：2022-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehwan MOON ,  Jinseong HEO ,  Seunggeol NAM ,  Hagyoul BAE ,  Hyunjae LEE

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06N3/04

Abstract: Provided is a neural network device including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting the first direction, and a plurality of memory cells arranged at points where the plurality of word lines and the plurality of bit lines intersect one another. Each of the plurality of memory cells includes at least two ferroelectric memories connected in parallel along a word line corresponding to each of the plurality of memory cells.

公开(公告)号：US20230155026A1

公开(公告)日：2023-05-18

申请号：US17986237

申请日：2022-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hagyoul BAE ,  Dukhyun CHOE ,  Jinseong HEO ,  Yunseong LEE ,  Seunggeol NAM ,  Hyunjae LEE

IPC: H01L29/78 ,  H01L27/108 ,  H01L27/24 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L27/10805 ,  H01L27/2436 ,  H01L29/516 ,  H01L29/7833 ,  H01L29/6684

Abstract: Provided are a semiconductor device and a semiconductor apparatus including the semiconductor device. The semiconductor device includes a substrate having a channel layer comprising a dopant, a ferroelectric layer on the channel layer; and a gate on the ferroelectric layer. The channel layer has a doping concentration of 1×1015 cm−3 to 1×1021 cm−3.

公开(公告)号：US20230068904A1

公开(公告)日：2023-03-02

申请号：US17876979

申请日：2022-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Yunseong LEE ,  Hyangsook LEE ,  Sanghyun JO ,  Seunggeol NAM ,  Taehwan MOON ,  Hagyoul BAE ,  Eunha LEE ,  Junho LEE

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/10

Abstract: An electronic device includes: a substrate including a source, a drain, and a channel between the source and the drain; a gate electrode arranged above the substrate and facing the channel, the gate electrode being apart from the channel in a first direction; and a ferroelectric thin film structure between the channel and the gate electrode, the ferroelectric thin film structure including a first ferroelectric layer, a crystallization barrier layer including a dielectric material, and a second ferroelectric layer, which are sequentially arranged from the channel in the first direction. The average of sizes of crystal grains of the first ferroelectric layer may be less than or equal to the average of sizes of crystal grains of the second ferroelectric layer, and owing to small crystal grains, dispersion of performance may be improved.

公开(公告)号：US20230068706A1

公开(公告)日：2023-03-02

申请号：US17896481

申请日：2022-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hagyoul BAE ,  Jinseong HEO ,  Seunggeol NAM ,  Taehwan MOON ,  Yunseong LEE

IPC: H01L27/24 ,  H01L27/11582 ,  H01L27/11597

Abstract: A non-volatile memory device is provided. The nonvolatile memory device includes a metal pillar, a channel layer separated from the metal pillar and surrounding a side surface of the metal pillar, a source arranged on one end of the channel layer, a drain arranged on the other end of the channel layer, a gate insulating layer surrounding a side surface of the channel layer, and a plurality of insulating elements and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer and surrounding a side surface of the gate insulating layer.

公开(公告)号：US20220140104A1

公开(公告)日：2022-05-05

申请号：US17515969

申请日：2021-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Yunseong LEE ,  Seunggeol NAM ,  Hagyoul BAE ,  Taehwan MOON ,  Sanghyun JO

IPC: H01L29/51 ,  H01L29/78

Abstract: Provided is a ferroelectric semiconductor device including a ferroelectric layer and two or more electrode layers. The semiconductor device may include a first electrode layer and a second electrode layer which have thermal expansion coefficients less than the thermal expansion coefficient of the ferroelectric layer. The difference between the thermal expansion coefficients of the second electrode layer and the ferroelectric layer may be greater than the difference between the thermal expansion coefficients of the first electrode layer and the ferroelectric. The second electrode layer may have a thickness greater than the thickness of the first electrode layer.