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    ELECTRONIC DEVICE INCLUDING FERROELECTRIC THIN FILM STRUCTURE
    3.
    发明申请
    ELECTRONIC DEVICE INCLUDING FERROELECTRIC THIN FILM STRUCTURE 有权

    公开(公告)号：US20230062878A1

    公开(公告)日：2023-03-02

    申请号：US17894504

    申请日：2022-08-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinseong HEO ,  Yunseong LEE ,  Hyangsook LEE ,  Sanghyun JO ,  Seunggeol NAM ,  Taehwan MOON ,  Hagyoul BAE ,  Eunha LEE ,  Junho LEE

    IPC: H01L29/78 ,  H01L29/51

    Abstract: An electronic device includes: a substrate including a source, a drain, and a channel between the source and the drain; a gate electrode arranged above the substrate and facing the channel, the gate electrode being apart from the channel in a first direction; and a ferroelectric thin film structure between the channel and the gate electrode, the ferroelectric thin film structure including a first ferroelectric layer, a crystallization barrier layer including a dielectric material, and a second ferroelectric layer, which are sequentially arranged from the channel in the first direction. The average of sizes of crystal grains of the first ferroelectric layer may be less than or equal to the average of sizes of crystal grains of the second ferroelectric layer, and owing to small crystal grains, dispersion of performance may be improved.

    NON-VOLATILE CONTENT ADDRESSABLE MEMORY DEVICE HAVING SIMPLE CELL CONFIGURATION AND OPERATING METHOD OF THE SAME
    4.
    发明申请
    NON-VOLATILE CONTENT ADDRESSABLE MEMORY DEVICE HAVING SIMPLE CELL CONFIGURATION AND OPERATING METHOD OF THE SAME 有权

    公开(公告)号：US20220351776A1

    公开(公告)日：2022-11-03

    申请号：US17540675

    申请日：2021-12-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seunggeol NAM ,  Jinseong HEO ,  Taehwan MOON ,  Hagyoul BAE

    IPC: G11C15/04

    Abstract: Disclosed are a non-volatile content addressable memory device having a simple cell configuration and/or an operating method thereof. The non-volatile content addressable memory device includes a plurality of unit cells, wherein each of the plurality of unit cells consists of or includes a first ferroelectric transistor and a second ferroelectric transistor The first and second ferroelectric transistors are of different types such as different electrical types from each other. The first and second ferroelectric transistors may be connected in series or in parallel to each other. The first and second ferroelectric transistors may share one word line and one match line. The first and second ferroelectric transistors may share one search line. One of the first and second ferroelectric transistors may be connected to a search line and the other one may be connected to a bar search line. The first and second ferroelectric transistors may share one match line.

    NON-VOLATILE CONTENT ADDRESSABLE MEMORY DEVICE HAVING SIMPLE CELL CONFIGURATION AND OPERATING METHOD OF THE SAME
    7.
    发明公开
    NON-VOLATILE CONTENT ADDRESSABLE MEMORY DEVICE HAVING SIMPLE CELL CONFIGURATION AND OPERATING METHOD OF THE SAME 审中-公开

    公开(公告)号：US20240265967A1

    公开(公告)日：2024-08-08

    申请号：US18621853

    申请日：2024-03-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seunggeol NAM ,  Jinseong HEO ,  Taehwan MOON ,  Hagyoul BAE

    IPC: G11C15/04

    CPC classification number: G11C15/046

    Abstract: Disclosed are a non-volatile content addressable memory device having a simple cell configuration and/or an operating method thereof. The non-volatile content addressable memory device includes a plurality of unit cells, wherein each of the plurality of unit cells consists of or includes a first ferroelectric transistor and a second ferroelectric transistor The first and second ferroelectric transistors are of different types such as different electrical types from each other. The first and second ferroelectric transistors may be connected in series or in parallel to each other. The first and second ferroelectric transistors may share one word line and one match line. The first and second ferroelectric transistors may share one search line. One of the first and second ferroelectric transistors may be connected to a search line and the other one may be connected to a bar search line. The first and second ferroelectric transistors may share one match line.

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220173255A1

    公开(公告)日：2022-06-02

    申请号：US17461034

    申请日：2021-08-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinseong HEO ,  Taehwan MOON ,  Hagyoul BAE ,  Seunggeol NAM ,  Sangwook KIM ,  Kwanghee LEE

    IPC: H01L29/86 ,  H01L27/115 ,  H01L51/05 ,  H01L27/28

    Abstract: A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

    THREE-DIMENSIONAL FERROELECTRIC MEMORY DEVICE
    10.
    发明公开
    THREE-DIMENSIONAL FERROELECTRIC MEMORY DEVICE 审中-公开

    公开(公告)号：US20240015983A1

    公开(公告)日：2024-01-11

    申请号：US18340560

    申请日：2023-06-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinseong HEO ,  Taehwan MOON ,  Seunggeol NAM ,  Hyunjae LEE

    IPC: H10B53/20 ,  H10B53/30

    CPC classification number: H10B53/20 ,  H10B53/30

    Abstract: A three-dimensional (3D) ferroelectric memory device may include a plurality of gate electrodes stacked on a substrate, a plurality of ferroelectric layers in contact with the plurality of gate electrodes, a plurality of intermediate electrodes in contact with the plurality of ferroelectric layers, a gate insulating layer in contact with the plurality of intermediate electrodes, and a channel layer in contact with the gate insulating layer. Widths of the intermediate electrodes may be greater than widths of the ferroelectric layers in contact with the intermediate electrodes.

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