公开(公告)号：US20250142936A1

公开(公告)日：2025-05-01

申请号：US19006438

申请日：2024-12-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseong LEE ,  Jinseong HEO ,  Taehwan MOON ,  Seunggeol NAM ,  Dukhyun CHOE

IPC: H10D64/68 ,  H10B51/00 ,  H10B53/00

Abstract: A layer structure including a dielectric layer, a method of manufacturing the layer structure, and an electronic device including the layer structure are disclosed. The layer structure including a lower layer, a dielectric layer, and an upper layer sequentially stacked. The dielectric layer includes sequentially stacked first, second, and third layers, wherein one of the first layer or the third layer is a ferroelectric, the other one is an anti-ferroelectric, and the second layer is an oxide layer. In one example, the dielectric layer may further include a fourth layer on the third layer.

公开(公告)号：US20230207659A1

公开(公告)日：2023-06-29

申请号：US18179598

申请日：2023-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun JO ,  Sangwook Kim ,  Yunseong LEE ,  Jinseong HEO

IPC: H01L29/51 ,  H01L27/06

CPC classification number: H01L29/516 ,  H01L27/0629 ,  H01L28/60 ,  H01L29/513

Abstract: A ferroelectric structure includes a first polarization enhancement film on a ferroelectric film, wherein the ferroelectric film has a first net polarization in a first direction oriented from the ferroelectric film toward the first polarization enhancement film. The first polarization enhancement film has a second net polarization in a second direction crossing the first direction.

公开(公告)号：US20210305399A1

公开(公告)日：2021-09-30

申请号：US17208018

申请日：2021-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Yunseong LEE ,  Taehwan MOON ,  Sanghyun JO

IPC: H01L29/51 ,  H01L21/28

Abstract: An electronic device includes a seed layer including a two-dimensional (2D) material, and a ferroelectric layer on the seed layer. The ferroelectric layer is configured to be aligned in a direction in which a (111) crystal direction is perpendicular to a top surface of a substrate on which the seed layer is located and/or a top surface of the seed layer.

公开(公告)号：US20210167183A1

公开(公告)日：2021-06-03

申请号：US17154354

申请日：2021-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Yunseong LEE ,  Sanghyun JO ,  Keunwook SHIN ,  Hyeonjin SHIN

IPC: H01L29/51 ,  H01L21/02

Abstract: Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp2 bonding structure.

公开(公告)号：US20210036024A1

公开(公告)日：2021-02-04

申请号：US16943161

申请日：2020-07-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook KIM ,  Jinseong HEO ,  Yunseong LEE ,  Sanghyun JO

IPC: H01L27/12 ,  G06N3/063 ,  G06N3/08

Abstract: A semiconductor device includes a first transistor including a first channel layer of a first conductivity type, a second transistor provided in parallel with the first transistor and including a second channel layer of a second conductivity type, and a third transistor stacked on the first and second transistors. The third transistor may include a gate insulating film including a ferroelectric material. The third transistor may include third channel layer and a gate electrode that are spaced apart from each other in a thickness direction with the gate insulating film therebetween.

公开(公告)号：US20190016906A1

公开(公告)日：2019-01-17

申请号：US15944920

申请日：2018-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Sangwon KIM ,  Hyeonjin SHIN ,  Dongwook LEE ,  Seongjun PARK ,  Yunseong LEE ,  Seongjun JEONG ,  Alum JUNG

IPC: C09D7/63 ,  C07F3/02 ,  G03F7/16 ,  G03F7/20 ,  G03F7/38 ,  G03F7/32 ,  H01L21/311 ,  H01L21/3213

Abstract: Provided are a hardmask composition including a structure represented by Formula 1 and a solvent, a method of forming a pattern using the hardmask composition, and a hardmask formed from the hardmask composition. wherein in Formula 1, R1 to R8, X, and M are described in detail in the detailed description.

公开(公告)号：US20240196623A1

公开(公告)日：2024-06-13

申请号：US18531922

申请日：2023-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseong LEE ,  Jinseong HEO ,  Kihong KIM ,  Dukhyun CHOE ,  Hyunjae LEE ,  Sanghyun JO

IPC: H10B51/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B53/20

CPC classification number: H10B51/20 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H10B53/20

Abstract: An electronic device may include a conductive material layer, a ferroelectric layer covering the conductive material layer, and an electrode covering the ferroelectric layer. The ferroelectric layer may include a compound represented by HfxAyOz, where 0≤x≤1, 0≤y≤1, and 2(x+y)

公开(公告)号：US20240162337A1

公开(公告)日：2024-05-16

申请号：US18510063

申请日：2023-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Van Luan NGUYEN ,  Hyeonjin SHIN ,  Minsu SEOL ,  Yunseong LEE

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/778 ,  H01L29/41758 ,  H01L29/42364

Abstract: A semiconductor device including a two-dimensional material is provided. The semiconductor device may include a two-dimensional material layer having semiconductor properties, a self-assembled monolayer in which self-assembled molecules are packed side-by-side, the self-assembled monolayer being arranged on the two-dimensional material layer, and an oxide layer arranged on the self-assembled monolayer.

公开(公告)号：US20230253498A1

公开(公告)日：2023-08-10

申请号：US18303288

申请日：2023-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseong LEE ,  Jinseong HEO ,  Sangwook KIM ,  Taewan MOON ,  Sanghyun JO

IPC: H01L29/78 ,  H01L29/51 ,  H10B51/30

CPC classification number: H01L29/78391 ,  H01L29/516 ,  H10B51/30 ,  H01L21/02181

Abstract: Provided is a ferroelectric thin-film structure including a semiconductor substrate, a first ferroelectric layer on the semiconductor substrate, and a second ferroelectric layer on the semiconductor substrate. The second ferroelectric layer is spaced apart from the first ferroelectric layer and has a different dielectric constant from the first ferroelectric layer. The first ferroelectric layer and the second ferroelectric layer may be different from each other in terms of the amount of a dopant contained therein, and may exhibit different threshold voltages when applied to transistors.

公开(公告)号：US20230062878A1

公开(公告)日：2023-03-02

申请号：US17894504

申请日：2022-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Yunseong LEE ,  Hyangsook LEE ,  Sanghyun JO ,  Seunggeol NAM ,  Taehwan MOON ,  Hagyoul BAE ,  Eunha LEE ,  Junho LEE

IPC: H01L29/78 ,  H01L29/51

Abstract: An electronic device includes: a substrate including a source, a drain, and a channel between the source and the drain; a gate electrode arranged above the substrate and facing the channel, the gate electrode being apart from the channel in a first direction; and a ferroelectric thin film structure between the channel and the gate electrode, the ferroelectric thin film structure including a first ferroelectric layer, a crystallization barrier layer including a dielectric material, and a second ferroelectric layer, which are sequentially arranged from the channel in the first direction. The average of sizes of crystal grains of the first ferroelectric layer may be less than or equal to the average of sizes of crystal grains of the second ferroelectric layer, and owing to small crystal grains, dispersion of performance may be improved.