公开(公告)号：US10825862B2

公开(公告)日：2020-11-03

申请号：US16394139

申请日：2019-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghyun Cho ,  You-Jin Jung ,  Masayuki Terai ,  Jinchan Yun

IPC: H01L27/24 ,  H01L45/00

Abstract: A variable resistance memory device includes: a substrate including a peripheral region and a core region, the core region including a far region spaced apart from the peripheral region and a near region between the far region and the peripheral region; first conductive lines disposed on the substrate and extending in a first direction; second conductive lines disposed on the first conductive lines and extending in a second direction intersecting the first direction, and memory cells disposed between the first and second conductive lines on the core region. The memory cells include a near memory cell disposed on the near region, and a far memory cell disposed on the far region, wherein a resistance or threshold voltage of the near memory cell, controlling connection of each of the memory cells to a corresponding one of the second conductive lines, is different from that of the far memory cell.

公开(公告)号：US20160035545A1

公开(公告)日：2016-02-04

申请号：US14631083

申请日：2015-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kye Hyun Baek ,  Ohyung Kwon ,  Junghyun Cho ,  Haejoong Park

IPC: H01J37/32

CPC classification number: H01J37/32917 ,  H01J37/32807 ,  H01J37/3288

Abstract: Provided are methods and systems for managing semiconductor manufacturing equipment. A method may include preventive maintenance involving steps of disassembling, cleaning, and assembling parts of a chamber. The assembling of the parts may include checking whether the parts are correctly assembled, using reflectance and absorptivity of a high-frequency voltage applied to the parts.

Abstract translation: 提供了用于管理半导体制造设备的方法和系统。 一种方法可以包括预防性维护，其包括拆卸，清洁和组装室的部件的步骤。 部件的组装可以包括使用施加到部件的高频电压的反射率和吸收率来检查部件是否被正确组装。

公开(公告)号：US20240355709A1

公开(公告)日：2024-10-24

申请号：US18637022

申请日：2024-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kitae Park ,  Seonkyu Kim ,  Seungmin Baek ,  Joonseok Oh ,  Joohyung Lee ,  Junghyun Cho

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/16 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1815

Abstract: A semiconductor package includes a base chip, a first semiconductor chip on the base chip, and a first fillet layer between the base chip and the first semiconductor chip. The base chip includes a base substrate, a plurality of through-electrodes penetrating through the base substrate, a protective layer surrounding the plurality of through-electrodes and covering an upper surface of the base substrate, and a plurality of trenches vertically penetrating the protective layer. The plurality of through-electrodes form a transistor area on the base substrate, and the plurality of trenches include first trenches disposed between adjacent through-vias in the transistor area and second trenches disposed in an outer side portion of the transistor area.

公开(公告)号：US11653504B2

公开(公告)日：2023-05-16

申请号：US17232865

申请日：2021-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Song Yi Kim ,  Junghyun Cho

IPC: H10B63/00 ,  G11C13/00 ,  G11C7/12 ,  G11C7/18 ,  G11C8/14

CPC classification number: H10B63/84 ,  G11C7/12 ,  G11C7/18 ,  G11C8/14 ,  G11C13/0026 ,  G11C13/0028 ,  H10B63/30 ,  H10N70/231 ,  H10N70/253 ,  H10N70/841

Abstract: A semiconductor memory device including a device isolation layer in a substrate to define first and second active portions, a first contact on the substrate, first and second memory cells spaced apart from the first contact in a first direction by first and second distances, respectively, first and second conductive lines connected to the first and second memory cells, respectively, and extending in a second direction, and first and second selection transistors respectively connected to the first and second conductive lines. A length of a bottom surface of a first gate electrode of the first selection transistor overlapping the first active portion in a third direction may be different from a length of a bottom surface of a second gate electrode of the second selection transistor overlapping the second active portion in the third direction.

公开(公告)号：US11322579B2

公开(公告)日：2022-05-03

申请号：US16661414

申请日：2019-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Song Yi Kim ,  Junghyun Cho

IPC: H01L49/02 ,  H01L23/522 ,  H01L27/24 ,  H01L23/528 ,  H01L45/00

Abstract: A semiconductor device includes a substrate and memory cell arrays arranged on the substrate in a first direction and second direction. The first direction and second direction are parallel to a top surface of the substrate and intersect each other. The memory cell arrays include a plurality of memory cells. A cell dummy pattern on the substrate is arranged between the memory cell arrays in at least one of the first direction and second direction and extends along a side of the memory cell arrays. A cell conductive pattern is included on the substrate. A cell contact plug is configured to connect the cell dummy pattern and the cell conductive pattern. The cell contact plug is arranged between the cell dummy pattern and the cell conductive pattern in a third direction that is perpendicular to the first direction and the second direction.

公开(公告)号：US20200286818A1

公开(公告)日：2020-09-10

申请号：US16723455

申请日：2019-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghyun Cho ,  Youngsik Hur ,  Youngkwan Lee ,  Jongrok Kim

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes: an interposer substrate including a core substrate and a connection structure, the core substrate having a cavity and having through-vias connecting upper and lower surfaces thereof, and the connection structure including an insulating member on the upper surface and a redistribution layer on the insulating member; a semiconductor chip on an upper surface of the connection structure and including connection pads connected to the redistribution layer; a passive component accommodated in the cavity; a first insulating layer disposed between the core substrate and the connection structure; a first wiring layer on the first insulating layer and connecting the through-vias and the passive component to the redistribution layer; a second insulating layer on the lower surface of the core substrate; and a second wiring layer on a lower surface of the second insulating layer and connected to the through-vias.

公开(公告)号：US20250054735A1

公开(公告)日：2025-02-13

申请号：US18595009

申请日：2024-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wookhyeon Kwon ,  Minnhoo Choi ,  Songyun Kang ,  Yongwoo Kim ,  Jaehyun Kim ,  Hansol Kim ,  Chulwoo Park ,  Jaehyun Soh ,  Dongkyu Shin ,  Deukho Lee ,  Hoontaek Lee ,  Junghyun Cho ,  Yangyeon Chu ,  Kaan Uzun

IPC: H01J37/32

Abstract: A system is described for protecting the edge region of a substrate during a plasma process. The system includes an outer ring with a plurality of outer uneven portions and an inner ring also with a plurality of inner uneven portions. The outer ring covers the edge region of the substrate. The inner ring may rotate around the center point of the outer ring. When the inner ring is rotated, each of the inner uneven portions and each the outer uneven portions may slide by each other to overlap and to form openings. Changes of the opening ratios in the gaps (or the overlap ratios of the inner and outer uneven portions) may change a thickness of a plasma sheath. Thus, the plasma sheath in an edge region of the substrate may be readily controlled.

公开(公告)号：US12112920B2

公开(公告)日：2024-10-08

申请号：US17715453

申请日：2022-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewon Jeong ,  Daebeom Lee ,  Juho Lee ,  Junghyun Cho

IPC: H01J37/32 ,  H01L21/3065

CPC classification number: H01J37/32183 ,  H01J37/32568 ,  H01L21/3065

Abstract: A plasma processing system includes a radio-frequency (RF) power source unit configured to generate three RF powers; a process chamber to which a process gas supplied and to which the RF powers are applied to generate a plasma; and an impedance matcher between the RF power source unit and the process chamber, the impedance matcher configured to adjust an impedance. The RF power source unit may include a first RF power source connected to a first electrode located in a lower portion of the process chamber to apply a first RF power having a first frequency, a second RF power source connected to the first electrode and to apply a second RF power having a second frequency, and a third RF power source connected to a second electrode located in an upper portion of the process chamber and to apply a third RF power having a third frequency.

公开(公告)号：US20240258242A1

公开(公告)日：2024-08-01

申请号：US18421284

申请日：2024-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kitae Park ,  Chiwan Song ,  Seungmin Baek ,  Joohyung Lee ,  Joonseok Oh ,  Junghyun Cho

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/20 ,  H01L25/105 ,  H01L25/18 ,  H10B80/00 ,  H01L24/19 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2225/1035 ,  H01L2924/01028 ,  H01L2924/01029

Abstract: A semiconductor package includes a package body, a fan-in-chip structure (FICS) in the package body, a first redistribution structure, and a second redistribution structure. The FICS includes a first chip having a front surface and a rear surface, a bridge wiring structure including a bridge wiring layer on the rear surface of the first chip, and a bridge pad electrically connected to the bridge wiring layer. The first redistribution structure is on a bottom surface of the package body and the front surface of the first chip and includes a first redistribution element. The second redistribution structure is on a top surface of the package body and the rear surface of the first chip and includes a second redistribution element electrically connected to the bridge wiring structure.

公开(公告)号：US20240212992A1

公开(公告)日：2024-06-27

申请号：US18453378

申请日：2023-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changheon Lee ,  Sangki Nam ,  Kuihyun Yoon ,  Kiho Lee ,  Sangho Lee ,  Sangheun Lee ,  Jaemin Rhee ,  Junghyun Cho ,  Seoyeon Choi

IPC: H01J37/32 ,  H01L21/683

CPC classification number: H01J37/32642 ,  H01J37/32715 ,  H01J37/3299 ,  H01L21/6833 ,  H01J2237/2007 ,  H01J2237/334

Abstract: Provided is a plasma processing apparatus including a substrate chuck in a chamber, a restriction ring surrounding an outer perimeter of the substrate chuck, a movable ring on the restriction ring, and an actuator configured to move the movable ring, wherein grooves formed in the restriction ring are opened or closed by movement of the movable ring. In addition, provided is a plasma processing method using the plasma processing apparatus.