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公开(公告)号:US20220302267A1
公开(公告)日:2022-09-22
申请号:US17496300
申请日:2021-10-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dukhyun CHOE , Jinseong HEO , Yunseong LEE , Sanghyun JO
Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate, a channel layer at least one of on or in the substrate, an insulation layer on the substrate, a ferroelectric layer on the insulation layer, a fixed charge layer on an interface between the insulation layer and the ferroelectric layer, the fixed charge layer including charges of a first polarity, and a gate on the ferroelectric layer.
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公开(公告)号:US20210091227A1
公开(公告)日:2021-03-25
申请号:US17026665
申请日:2020-09-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jinseong HEO , Sangwook KIM , Yunseong LEE , Sanghyun JO
Abstract: A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.
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公开(公告)号:US20210083121A1
公开(公告)日:2021-03-18
申请号:US17001979
申请日:2020-08-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jinseong HEO , Sangwook KIM , Yunseong LEE , Sanghyun JO , Hyangsook LEE
Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.
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14.
公开(公告)号:US20210074815A1
公开(公告)日:2021-03-11
申请号:US17087968
申请日:2020-11-03
Applicant: Samsung Electronics Co., Ltd.
Inventor: Keunwook SHIN , Hyeonjin SHIN , Yeonchoo CHO , Seunggeol NAM , Seongjun PARK , Yunseong LEE
IPC: H01L29/16 , H01L21/02 , C01B32/186
Abstract: Provided is a semiconductor device including graphene. The semiconductor device includes: a substrate including an insulator and a semiconductor; and a graphene layer configured to directly grow only on a surface of the semiconductor, wherein the semiconductor includes at least one of a group IV material and a group III-V compound.
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公开(公告)号:US20200055134A1
公开(公告)日:2020-02-20
申请号:US16391477
申请日:2019-04-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jinseong HEO , Yunseong LEE , Sanghyun JO
Abstract: Provided are a logic switching device and a method of manufacturing the same. The logic switching device may include a domain switching layer adjacent to a gate electrode. The domain switching layer may include a ferroelectric material region and an anti-ferroelectric material region. The domain switching layer may be a non-memory element. The logic switching device may include a channel, a source and a drain both connected to the channel, the gate electrode arranged to face the channel, and the domain switching layer provided between the channel and the gate electrode.
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公开(公告)号:US20240274714A1
公开(公告)日:2024-08-15
申请号:US18634295
申请日:2024-04-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sangwook KIM , Yunseong LEE , Sanghyun JO , Jinseong HEO
IPC: H01L29/78 , H01L21/28 , H01L21/8234 , H01L27/088 , H01L29/51 , H01L29/66
CPC classification number: H01L29/78391 , H01L21/28185 , H01L21/823412 , H01L21/823418 , H01L21/823437 , H01L27/088 , H01L29/513 , H01L29/516 , H01L29/517 , H01L29/6684
Abstract: An integrated circuit includes transistors respectively including channel layers in a substrate, source electrodes and drain electrodes respectively contacting both sides of the channel layers, gate electrodes on the channel layers, and ferroelectrics layers between the channel layers and the gate electrodes. Electrical characteristics of the ferroelectrics layers of at least two of the transistors are different. Accordingly, threshold voltages of the transistors are different from each other.
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公开(公告)号:US20240088256A1
公开(公告)日:2024-03-14
申请号:US18513042
申请日:2023-11-17
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jinseong HEO , Yunseong LEE , Taehwan MOON , Sanghyun JO
CPC classification number: H01L29/516 , H01L21/28158 , H01L29/40111
Abstract: An electronic device includes a seed layer including a two-dimensional (2D) material, and a ferroelectric layer on the seed layer. The ferroelectric layer is configured to be aligned in a direction in which a (111) crystal direction is perpendicular to a top surface of a substrate on which the seed layer is located and/or a top surface of the seed layer.
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公开(公告)号:US20240038890A1
公开(公告)日:2024-02-01
申请号:US18486493
申请日:2023-10-13
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jinseong HEO , Sangwook KIM , Yunseong LEE , Sanghyun JO
CPC classification number: H01L29/78391 , H01L29/40111 , G11C11/223 , H01L29/6684
Abstract: A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.
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公开(公告)号:US20230268439A1
公开(公告)日:2023-08-24
申请号:US18310022
申请日:2023-05-01
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yunseong LEE , Jinseong HEO , Sangwook KIM , Sanghyun JO
CPC classification number: H01L29/78391 , H01L29/513 , H01L29/516 , H01L29/517 , H01L29/42364 , H01L21/0228 , H01L21/022 , H01L29/6684 , H01L29/0847 , H01L29/40111 , H01L21/02175 , H01L21/02181 , H01L21/02189 , H10B51/30
Abstract: An electronic device includes a ferroelectric layer arranged on a channel region and a gate electrode arranged on the ferroelectric layer. The ferroelectric layer includes a plurality of first oxide monolayers and a second oxide monolayers that is arranged between the substrate and the gate electrode and include a material different from a material of the first oxide monolayers. The first oxide monolayers include oxide monolayers that are alternately formed and include materials different from one another.
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20.
公开(公告)号:US20230015172A1
公开(公告)日:2023-01-19
申请号:US17952699
申请日:2022-09-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: Taehwan MOON , Jinseong HEO , Sangwook KIM , Yunseong LEE
IPC: H01L49/02 , H01L51/05 , H01L29/78 , H01L21/02 , H01L29/40 , H01L27/11507 , H01L27/1159 , H01L29/49
Abstract: Disclosed are a thin film structure and an electronic device including the same. The disclosed thin film structure includes a dielectric material layer between a first material layer and a second material layer. The dielectric material layer includes a dopant in a matrix material having a fluorite structure. The dielectric material layer is uniformly doped with a low concentration of the dopant, and has ferroelectricity.
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