公开(公告)号：US20160322535A1

公开(公告)日：2016-11-03

申请号：US15212659

申请日：2016-07-18

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/22 ,  H01L33/12 ,  H01L29/20 ,  H01L29/778 ,  H01L29/66 ,  H01L29/205 ,  H01L33/06 ,  H01L33/10 ,  H01L21/02 ,  H01L33/00 ,  H01L33/32 ,  H01L29/34

CPC classification number: H01L33/22 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/02658 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L33/007 ,  H01L33/06 ,  H01L33/10 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L2933/0091

Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

公开(公告)号：US20160240739A1

公开(公告)日：2016-08-18

申请号：US15138415

申请日：2016-04-26

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Rakesh Jain ,  Jinwei Yang ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/22 ,  H01L33/06 ,  H01L33/12 ,  G06F17/50 ,  H01L33/00 ,  H01L33/32

CPC classification number: H01L33/22 ,  G06F17/5068 ,  G06F2217/12 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02617 ,  H01L21/02639 ,  H01L21/0265 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/12 ,  H01L33/32 ,  H01L2224/16225

Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.

Abstract translation: 提供了用于改善半导体层的生长的图案化表面，例如III族氮化物基半导体层。 图案化表面可以包括一组基本平坦的顶表面和多个开口。 每个基本上平坦的顶表面可以具有小于约0.5纳米的均方根粗糙度，并且开口可以具有在约0.1微米和5微米之间的特征尺寸。 基本平坦的顶表面中的一个或多个可以基于目标辐射进行图案化。

公开(公告)号：US09385271B2

公开(公告)日：2016-07-05

申请号：US14721082

申请日：2015-05-26

Applicant: Sensor Electronic Technology, Inc.

Inventor： Michael Shur ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Remigijus Gaska ,  Jinwei Yang

IPC: H01L33/06 ,  H01L33/32 ,  B82Y10/00 ,  H01L21/02 ,  H01L29/15 ,  H01L33/00 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L33/06 ,  B82Y10/00 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/15 ,  H01L29/2003 ,  H01L29/778 ,  H01L33/0025 ,  H01L33/32

Abstract: A device including one or more layers with lateral regions configured to facilitate the transmission of radiation through the layer and lateral regions configured to facilitate current flow through the layer is provided. The layer can comprise a short period superlattice, which includes barriers alternating with wells. In this case, the barriers can include both transparent regions, which are configured to reduce an amount of radiation that is absorbed in the layer, and higher conductive regions, which are configured to keep the voltage drop across the layer within a desired range.

公开(公告)号：US09269788B2

公开(公告)日：2016-02-23

申请号：US13775038

申请日：2013-02-22

Applicant: Sensor Electronic Technology, Inc.

Inventor： Remigijus Gaska ,  Michael Shur ,  Jinwei Yang ,  Alexander Dobrinsky ,  Maxim S Shatalov

IPC: H01L21/338 ,  H01L29/66 ,  H01L29/778 ,  H01L21/285 ,  H01L29/40 ,  H01L29/45 ,  H01L33/00 ,  H01L29/205 ,  H01L33/14 ,  H01L29/15 ,  H01L29/20 ,  H01L29/201 ,  H01L33/40

CPC classification number: H01L29/452 ,  H01L21/28575 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/401 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/737 ,  H01L29/778 ,  H01L29/7786 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/14 ,  H01L33/32 ,  H01L33/40 ,  H01L33/405 ,  H01L2933/0016

Abstract: A solution for forming an ohmic contact to a semiconductor layer is provided. A masking material is applied to a set of contact regions on the surface of the semiconductor layer. Subsequently, one or more layers of a device heterostructure are formed on the non-masked region(s) of the semiconductor layer. The ohmic contact can be formed after the one or more layers of the device heterostructure are formed. The ohmic contact formation can be performed at a processing temperature lower than a temperature range within which a quality of a material forming any semiconductor layer in the device heterostructure is damaged.

Abstract translation: 提供了用于形成与半导体层的欧姆接触的解决方案。 掩模材料被施加到半导体层表面上的一组接触区域。 随后，在半导体层的非掩蔽区域上形成一层或多层器件异质结构。 欧姆接触可以在形成器件异质结构的一个或多个层之后形成。 欧姆接触形成可以在低于在器件异质结构中形成任何半导体层的材料的质量被损坏的温度范围的处理温度下进行。

公开(公告)号：US20150108428A1

公开(公告)日：2015-04-23

申请号：US14519230

申请日：2014-10-21

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Rakesh Jain ,  Jinwei Yang ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L29/15 ,  H01L33/00 ,  H01L33/06 ,  H01L29/06 ,  H01L33/24 ,  H01L33/32 ,  H01L29/20 ,  H01L29/205 ,  H01L21/02 ,  H01L33/12

CPC classification number: H01L29/151 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L33/0075 ,  H01L33/12

Abstract: A heterostructure for use in an electronic or optoelectronic device is provided. The heterostructure includes one or more composite semiconductor layers. The composite semiconductor layer can include sub-layers of varying morphology, at least one of which can be formed by a group of columnar structures (e.g., nanowires). Another sub-layer in the composite semiconductor layer can be porous, continuous, or partially continuous.

Abstract translation: 提供了用于电子或光电子器件的异质结构。 异质结构包括一个或多个复合半导体层。 复合半导体层可以包括不同形态的子层，其中至少一个可以由一组柱状结构（例如，纳米线）形成。 复合半导体层中的另一个子层可以是多孔的，连续的或部分连续的。

公开(公告)号：US20150083994A1

公开(公告)日：2015-03-26

申请号：US14493388

申请日：2014-09-23

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Maxim S. Shatalov ,  Jinwei Yang ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/00 ,  H01L33/12 ,  H01L33/14 ,  H01L33/06

CPC classification number: H01L33/0025 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/04 ,  H01L33/06 ,  H01L33/12 ,  H01L33/145 ,  H01L33/32

Abstract: Heterostructures for use in optoelectronic devices are described. One or more parameters of the heterostructure can be configured to improve the reliability of the corresponding optoelectronic device. The materials used to create the active structure of the device can be considered in configuring various parameters the n-type and/or p-type sides of the heterostructure.

Abstract translation: 描述了用于光电子器件的异质结构。 可以配置异质结构的一个或多个参数以提高相应光电器件的可靠性。 在构造异质结构的n型和/或p型侧的各种参数时，可以考虑用于形成器件的有源结构的材料。

公开(公告)号：US20140239312A1

公开(公告)日：2014-08-28

申请号：US14189012

申请日：2014-02-25

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Alexander Dobrinsky ,  Alexander Lunev ,  Rakesh Jain ,  Jinwei Yang ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/32

CPC classification number: H01L33/0025 ,  H01L33/0075 ,  H01L33/10 ,  H01L33/32 ,  H01L33/46 ,  H01S5/0224

Abstract: A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher.

Abstract translation: 提供包括多个不均匀区域的半导体层。 每个不均匀区域具有与形成半导体层的材料不同的一个或多个属性。 不均匀区域可以包括基于具有目标波长的辐射配置的一个或多个区域。 这些区域可以包括透明和/或反射区域。 不均匀区域还可以包括具有比基于辐射的区域的电导率更高的导电率的一个或多个区域，例如至少高10％。

公开(公告)号：US20140113389A1

公开(公告)日：2014-04-24

申请号：US14060173

申请日：2013-10-22

Applicant: Sensor Electronic Technology, Inc.

Inventor： Igor Agafonov ,  Jinwei Yang ,  Michael Shur ,  Remigijus Gaska

IPC: H01L21/02 ,  H01L21/66

CPC classification number: H01L21/0262 ,  C23C16/455 ,  C23C16/4584 ,  C23C16/52 ,  H01L22/12 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A solution for manufacturing semiconductors is provided. An embodiment provides a chemical vapor deposition reactor, which includes a chemical vapor deposition chamber. A substrate holder located in the chemical vapor deposition chamber can be rotated about its own axis at a first angular speed, and a gas injection component located in the chemical vapor deposition chamber can be rotated about an axis of the gas injection component at a second angular speed. The angular speeds are independently selectable and can be configured to cause each point on a surface of a substrate wafer to travel in an epicyclical trajectory within a gas flow injected by the gas injection component. An angle between the substrate holder axis and the gas injection component axis and/or a distance between the substrate holder axis and the gas injection component axis can be controlled variables.

Abstract translation: 提供制造半导体的解决方案。 实施例提供了一种化学气相沉积反应器，其包括化学气相沉积室。 位于化学气相沉积室中的衬底保持器可以以其第一角速度围绕其自身的轴线旋转，并且位于化学气相沉积室中的气体注入组件可以围绕气体注入部件的轴线以第二角度 速度。 角速度是可独立选择的，并且可以被配置成使得衬底晶片的表面上的每个点在由气体注入部件注入的气流中的行星轨迹中行进。 衬底保持器轴线和气体注入部件轴线之间的角度和/或衬底保持器轴线和气体注入部件轴线之间的距离可以是受控变量。

公开(公告)号：US20130193480A1

公开(公告)日：2013-08-01

申请号：US13756806

申请日：2013-02-01

Applicant: Sensor Electronic Technology, Inc.

Inventor： Wenhong Sun ,  Rakesh Jain ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Remigijus Gaska ,  Michael Shur

IPC: H01L21/02 ,  H01L29/06

CPC classification number: H01L21/02587 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/0684 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/16

Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer. One or more of a set of growth conditions, a thickness of one or both of the layers, and/or a lattice mismatch between the layers can be configured to create a target level of compressive and/or shear stress within a minimum percentage of the interface between the layers.

Abstract translation: 提供了一种用于制造半导体结构的解决方案。 半导体结构包括使用一组外延生长周期在衬底上生长的多个半导体层。 在每个外延生长周期期间，生长具有拉伸应力或压缩应力之一的第一半导体层，然后直接在第一半导体层上生长具有另一个的拉伸应力或压缩应力的第二半导体层。 一组生长条件中的一个或多个层中的一个或两个的厚度和/或层之间的晶格失配可以被配置为在最小百分比的范围内产生压缩和/或剪切应力的目标水平 层之间的界面。

公开(公告)号：USRE48943E1

公开(公告)日：2022-02-22

申请号：US16814607

申请日：2020-03-10

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Maxim S. Shatalov ,  Jinwei Yang ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/06 ,  H01L33/00 ,  H01L33/12 ,  H01L33/04 ,  H01L33/32 ,  H01L33/14

Abstract: Heterostructures for use in optoelectronic devices are described. One or more parameters of the heterostructure can be configured to improve the reliability of the corresponding optoelectronic device. The materials used to create the active structure of the device can be considered in configuring various parameters the n-type and/or p-type sides of the heterostructure.