公开(公告)号：JP2000086216A

公开(公告)日：2000-03-28

申请号：JP25551598

申请日：1998-09-09

Applicant: TOSHIBA CORP

Inventor： CHO TOSHI ,  SAKAI TADASHI ,  ONO TOMIO ,  SAKUMA HISASHI

IPC: H01J9/02 ,  C01B31/02 ,  C23C16/26 ,  H01J1/304

Abstract: PROBLEM TO BE SOLVED: To obtain a stable large emission current by applying enough voltage on each emitter. SOLUTION: After a SiO2 film 2 and a gate layer 3 formed on a silicon substrate 1 have been patterned, an Fe thin film 5 is formed by sputtering and Fe dots 6 are formed simultaneously on the exposed surface of the silicon substrate 1. While a magnetic field is applied using an electromagnet 7 on the Fe dots 6 in the perpendicular direction to the silicon substrate 1 to attract the Fe dots 6, carbon nanotubes 8 are selectively grown between the Fe dots 6 and the silicon substrate 1 to form emitter electrodes.

公开(公告)号：JPH09204874A

公开(公告)日：1997-08-05

申请号：JP1103396

申请日：1996-01-25

Applicant: TOSHIBA CORP

Inventor： SAKAI TADASHI ,  ONO TOMIO ,  CHO TOSHI

IPC: H01J1/304 ,  H01J9/02 ,  H01J1/30

Abstract: PROBLEM TO BE SOLVED: To enhance the reproducibility of an emitter shape using Si as the material and accomplish a high gate insulativeness. SOLUTION: An n-type Si board 13 is equipped with an emitter 14 whose side face has a conical shape in an arc of circle. The side face of the emitter 14 is restricted by a Si oxide insulative layer 18 formed in the surface of the board 13. The insulative layer 18 is formed by such a process that the p-region in the surface of the board 13 is turned porous by means of positive electrode chemical formation, followed by heat oxidation. The insulative layer 18 and a gate electrode 16 provided over it are equipped with a recess 18a and opening 16a as mating with the foremost part 14a of the emiter 14. The diameter of the opening 16a is set to half the diameter of the bottom part of the emitter 14, while the depth of the recess 18a is set so that more than one half of the lower part of the emitter 14 is embedded in the insulative layer 18.

公开(公告)号：JPH09185941A

公开(公告)日：1997-07-15

申请号：JP35214995

申请日：1995-12-28

Applicant: TOSHIBA CORP

Inventor： ONO TOMIO ,  SAKAI TADASHI ,  CHO TOSHI ,  NAKAMOTO MASAYUKI

IPC: H01J9/02 ,  H01J1/30 ,  H01J1/304 ,  H01J29/04 ,  H01J31/12 ,  H01L21/8234 ,  H01L27/088

Abstract: PROBLEM TO BE SOLVED: To provide an electron emission device in which manufacturing is easy without deteriorating the integration degree of an emitter. SOLUTION: An electron emission device has a junction FET, and in the junction FET, an n -type layer 12 formed on the rear face of a Si substrate 11 becomes a source region, an emitter 20 becomes a drain region, and a p -type region 151 surrounding an (n)channel region 152 becomes a gate. When an voltage applied to an electrode 17 is adjusted, the width of a depletion layer extending from the pn junction of the M-type region 151 and n-type channel region 152 into the channel region 152 is changed. Accordingly, by adjusting the applied voltage to the electrode 17, an electron current approaching from the n -type layer 12 to the tip of the emitter 20 can be controlled.

公开(公告)号：JP2002150921A

公开(公告)日：2002-05-24

申请号：JP2000339481

申请日：2000-11-07

Applicant: TOSHIBA CORP

Inventor： SAKAI TADASHI ,  ONO TOMIO ,  CHO TOSHI ,  SAKUMA HISASHI

IPC: H01J29/04 ,  H01J1/304 ,  H01J19/24 ,  H01J21/10 ,  H01J31/12

Abstract: PROBLEM TO BE SOLVED: To provide a field emission type cold cathode that will function, even if defective elements exist partially. SOLUTION: In the field emission type cathode that is comprised of an emitter array in which emitters 3 are arranged on the two dimensional face, a laminate 4 that covers the above emitter array be exposing the top end of the emitters 3, and a gate electrode layer 7 that is formed on the laminated 4, so as to surround each top end part of the emitters 3, the gate electrode layers 7 are connected to each other by a fuse electrode layer 8 that is blown out by the heat of short-circuit current.

公开(公告)号：JP2001185018A

公开(公告)日：2001-07-06

申请号：JP36707399

申请日：1999-12-24

Applicant: TOSHIBA CORP

Inventor： ONO TOMIO ,  SAKAI TADASHI ,  SAKUMA HISASHI ,  CHO TOSHI

IPC: H01J9/02 ,  H01J1/304

Abstract: PROBLEM TO BE SOLVED: To provide an electron emission element having a small potential drop and electron emission of a lower threshold value and a method of manufacturing the same. SOLUTION: At outer periphery of an emitter of which a sharpened tip consists of carbonaceous electron emission substance such as diamond 16 or the like of convex shape 19, a thin conductive layer 15 is installed to expose the tip of the emitter.

公开(公告)号：JP2001176377A

公开(公告)日：2001-06-29

申请号：JP36159799

申请日：1999-12-20

Applicant: TOSHIBA CORP

Inventor： SAKUMA HISASHI ,  ONO TOMIO ,  SAKAI TADASHI ,  CHO TOSHI

IPC: H01J9/02 ,  H01J1/304

Abstract: PROBLEM TO BE SOLVED: To facilitate impurity diffusion or doping into diamond and to increase a doping effect. SOLUTION: Into a supporting substrate, for example Si substrate 101 to make up diamond, a high-concentration boron is diffused by using an ion- implanting technology. Or, phosphorus is diffused into another area. By forming diamond 106 by the supporting substrate into which impurities have been diffused, diffusion of the impurities from the supporting substrate occurs in the initial process of the formation. This technology facilitates the diffusion of impurities into diamond 106, and enables to make up diffusion areas of many kinds of diffusion areas of impurities on the same surface.

公开(公告)号：JP2000277000A

公开(公告)日：2000-10-06

申请号：JP8189399

申请日：1999-03-25

Applicant: TOSHIBA CORP

Inventor： ONO TOMIO ,  SAKAI TADASHI ,  NAKAYAMA KAZUYA ,  CHO TOSHI

IPC: H01J1/304 ,  H01J9/02

Abstract: PROBLEM TO BE SOLVED: To easily emit electrons and resolve a problem of a high operating voltage by forming a projection, which is sharpened at the tip and is made of a carbonic electron emitting material, on top of a lug formed on a conductive structural substrate. SOLUTION: A thermal oxidation SiO2 layer 24 is formed on an n-type Si substrate 21 by dry oxidation, resist 28 is applied on it by spin coating, patterning such as exposure and development is applied, and the thermal oxidation SiO2 layer 24 is etched by an NH4/HF mixed aqueous solution to form a mask 22. The thermal oxidation SiO2 layer 24 is removed by etching, and a projection 25 of a carbonic electron emitting material is selectively grown only on top of a lug 23 by a hot filament CVD method. A SiO2 layer 26 as an insulating layer and a Mo layer 27 as a gate layer are formed, the resist 28 is applied, and the tip of an emitter is exposed by ashing. The projection 25 is exposed, the resist 28 is removed, and the gated emitter coated with the carbonic electron emitting material is obtained.

公开(公告)号：JP2000251616A

公开(公告)日：2000-09-14

申请号：JP4980399

申请日：1999-02-26

Applicant: TOSHIBA CORP

Inventor： CHO TOSHI ,  SAKAI TADASHI ,  ONO TOMIO ,  SAKUMA HISASHI

IPC: H01J9/02 ,  H01J1/304

Abstract: PROBLEM TO BE SOLVED: To ensure a low voltage drive and a large discharge current by implementing selection of material at each stage of implantation of electron back contact, transportation in an emitter and field emission to the vacuum through a diamond, under proper conditions. SOLUTION: A silicon substrate 12, with a mold is formed by anishotropic etching on a silicon substrate 11, then an insulating oxide film 13 is formed, and thereonto a carbon nanotube thin film 14 is filled in the mold. Thereafter, the transfer to a substrate having an Fe thin film 15 deposited thereon, the substrate is etched, and thereby an emitter array 17, an SiO2 insulation film 18, a silicon gate layer 19 are respectively formed. Then, irradiation of a laser beam is performed by a CO2 laser 110, whose output power is 3 kW. Successively, heat treatment at 900 deg.C is carried out to form a tip of diamond. Finally, an anode electrode 12 is formed.

公开(公告)号：JPH0982215A

公开(公告)日：1997-03-28

申请号：JP23221195

申请日：1995-09-11

Applicant: TOSHIBA CORP

Inventor： SAKAI TADASHI ,  ONO TOMIO ,  CHO TOSHI

IPC: H01J9/02 ,  H01J1/30 ,  H01J1/304 ,  H01J31/12

Abstract: PROBLEM TO BE SOLVED: To provide a uniform and reproductive vacuum micro element with a gate conductive layer electrically insulated and arranged around a quantum size of thin terminal in such a manner that the short small diameter of the opening of an emitter is equal to or less than a shortest distance between emitter and gate metals. SOLUTION: A Si substrate 1 with n-type impurities doped at a high concentration is thermally oxidized to form a thermally oxidized film 2 of thickness 1.5μm, e.g. on the surface. Then, a 0.2μm thick MO as a gate conductive layer 3 is spattered all over and a 1.0μm thick SiN film 4 is laminated thereon with CVD. An array-patterned photoresist mask with an 2μm diameter of circular opening is formed and laminated films are etched in sequence by using PIE, antimony fluoride etching to expose the Si surface. This is anode-formed in hydrofluoric acid to make the surface porous. Only the shape of the end of an emitter is sharpened so that an obtained element has no leak current to a gate at 1μA per unit opening when 200V voltage is applied to an anode.

公开(公告)号：JPH0897398A

公开(公告)日：1996-04-12

申请号：JP23083794

申请日：1994-09-27

Applicant: TOSHIBA CORP

Inventor： CHO TOSHI ,  SAKAI TADASHI ,  SUZUKI TAKEAKI ,  TAKAHASHI SHIGEKI

IPC: H01L29/06 ,  H01L29/66

Abstract: PURPOSE: To form quantum wires or quantum dots having an extremely steep quantum potential barrier on a substrate without giving damages to the substrate by a method where n-type semiconductor quantum wires or quantum dots are interposed between potential barriers of a porous semiconductor. CONSTITUTION: Phosphor impurities of high concentration are doped by an FIB ion implantation of a p-type impurity silicon substrate 1 of which the surface is processed, and wires 2 of an n-type region are formed in a p-type region. Next, it is dipped in a hydrofluoric acid solution and optically formed by an Xe lamp irradiation. Then, the p-type region is selectively etched as the anode and turned to a porous silicon layer 3 wide in a band gap. At this time, the n-type wires 2 are not etched to become a quantum wires, and porous silicon layers 3 work as quantum potential barriers. As described above, by a technique not using processes such as transfer, exposure to light, development or the like of patterns, a quantum wire array excellent in controllability of the wire width can be realized.