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公开(公告)号：JPS61156588A
公开(公告)日：1986-07-16
申请号：JP27830484
申请日：1984-12-27
Applicant: TOSHIBA CORP , TOSHIBA AUDIO VIDEO ENG
Inventor： TANAKA SHUICHI , KANESHIGE TOSHIHIKO
Abstract: PURPOSE:To execute automatically reproduction in a desired sequence at the time of recording by recording plural information in accordance with an order of recorder, and on the other hand, storing separated that after which information a reservation recording area exists, in a storage means, and storing a reproducing sequence by a start track address. CONSTITUTION:When the first reservation track number TR1 is set between recording information A and B, in a data array of an index use data storing circuit 29, SA1, SA2, and EA1, EA2 become each start track address of the information A, B, and each end track address, respectively. Information D records the information A, B, and thereafter, at the time of reproduction, the reproduction is executed in order of the information A, D and, B. As for an array of a recording area on a tape 10, recording is executed in order of the information A, B. In case of a reproducing mode, a start tack address and an end track address of the information D are read out, the former and the latter are stored in a temporary storing circuit 288 and a temporary storing circuit 282, respectively, a tape feed to the start track address is executed and the information D is reproduced, and when it is ended, subsequently, an index data of the third line is read out and the information B is reproduced.
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公开(公告)号：JPS61153802A
公开(公告)日：1986-07-12
申请号：JP27830384
申请日：1984-12-27
Applicant: TOSHIBA CORP , TOSHIBA AUDIO VIDEO ENG
Inventor： KANESHIGE TOSHIHIKO , TANAKA SHUICHI
Abstract: PURPOSE:To improve the utilization efficiency of a magnetic tape more by adjusting the write time in the tape sliding contact time of a magnetic head and thus setting a recording aera of two bands on the magnetic tape. CONSTITUTION:When signals are recorded in the recording area 11 of the magnetic tape 10, the tape is run in a direction A1 and write control pulses (b) are generated to supply signals to magnetic heads AM and BM. Consequently, recording tracks 11Aare formed in the recording area 11 by the heads AM and BM alternately. When the magnetic tape 10 travels as shown by an arrow B1, signals are written in a recording area 12, but write control pulses for selecting times t5 and t7 are generated. In this case, the rotating direction of a rotary magnetic head is invariably fixed, but the rotating direction is switched to the opposite direction of the recording of the recording area 11 when the recording of therecording area 12 is performed, and then track length L1 is equal to L2. Thus, the utilization efficiency of the magnetic tape is improved more.
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公开(公告)号：JP2010027181A
公开(公告)日：2010-02-04
申请号：JP2008190804
申请日：2008-07-24
Applicant: Toshiba Corp , 株式会社東芝
Inventor： TANAKA SHUICHI
Abstract: PROBLEM TO BE SOLVED: To provide a method for testing the nonvolatile semiconductor memory device, which can determine pass/fail of a function assigned to a redundant column area. SOLUTION: The method for testing the nonvolatile semiconductor memory device includes a step of writing down a protection flag limiting the operations to a block on a predetermined page within the target block, a step of reading the data on the page containing the protect flag to transfer it to the data register, a step of masking the data in the column address areas except the protect flag in the data transferred to the data register, a step of detecting the defective bits en bloc in the data register, and a step of registering as a defective block when defective bits are detected in the data register. COPYRIGHT: (C)2010,JPO&INPIT
Abstract translation: 要解决的问题：提供一种可以确定分配给冗余列区域的功能的通过/失败的非易失性半导体存储器件的测试方法。 解决方案：用于测试非易失性半导体存储器件的方法包括将限制操作的保护标志写入目标块中的预定页面上的块的步骤，读取包含保护的页面上的数据的步骤 标志将其传送到数据寄存器，对传送到数据寄存器的数据中除了保护标志之外的列地址区域中的数据进行屏蔽的步骤，检测数据寄存器中的缺陷位的步骤，以及步骤 当在数据寄存器中检测到有缺陷的位时，将其注册为缺陷块。 版权所有（C）2010，JPO＆INPIT
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公开(公告)号：JPH04129448A
公开(公告)日：1992-04-30
申请号：JP25154690
申请日：1990-09-20
Applicant: TOSHIBA CORP
Inventor： TANAKA SHUICHI , NAKAMURA MAKOTO , KODAMA TOMOKO
Abstract: PURPOSE:To attain accurate frame synchronization locking at all times by implementing insertion of a frame synchronizing signal and establishment of frame synchronization before differential logic coding and after differential logic decoding respectively. CONSTITUTION:A frame insertion means 1 is arranged before a differential logic coding means 2 in a sender side equipment to insert a frame synchronizing signal to a transmission digital signal before differential logic coding, and a frame synchronization means 10 is arranged after a differential logic decoding means 9 at a receiver side equipment to implement the processing for establishing frame synchronization. Then a signal selection means 8 is provided between an error correction decoding means 6 and the differential logic decoding means 9, and a reception digital signal not implementing error correction decoding is selected when the frame synchronization is not established and the reception digital signal after error correction decoding is selected while the frame synchronization is established to implement the differential logic decoding processing. Thus, frame synchronization is accurately taken.
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公开(公告)号：JPH03248625A
公开(公告)日：1991-11-06
申请号：JP4449590
申请日：1990-02-27
Applicant: TOSHIBA CORP
Inventor： TANAKA SHUICHI
IPC: H03M13/00
Abstract: PURPOSE:To attain the function monitor with simple constitution by providing an error correction coding circuit and an error correction decoding circuit selecting either the output of the error correction coding circuit or an external input and decoding the error correction code of the input. CONSTITUTION:When the execution of a function check of an error correction circuit 10 is commanded by a command input or the like from, e.g., an operation switch (not shown), a control section 11 uses a selector control means 11a to control a selector 5 to select a coding circuit 1. Thus, a coding signal resulting from error correction coding of a digital signal at the circuit 1 is given to a decoding circuit 2. Thus, the coding signal is decoded by the circuit 2 immediately and inputted to a comparator circuit 12 and the control section 11 monitors the result of comparison outputted from the comparator circuit 12. The result of comparison is monitored by using a fault discrimination circuit 11b and whether or not a digital signal outputted from the circuit 2 and an input digital signal to the circuit 1 are identical to each other is monitored.
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Patent Agency Ranking
公开(公告)号：JPH02244912A
公开(公告)日：1990-09-28
申请号：JP6380989
申请日：1989-03-17
Applicant: TOSHIBA CORP
Inventor： TANAKA SHUICHI , WATANABE TAICHI
Abstract: PURPOSE:To improve the shortening and equalizing accuracy of a leadingin time even when a system with a low bit rate is used by allowing an artificial BET detecting circuit or the like to artificially detect the quantity of waveform distortion generated by fading, and even if fading is generated and errors are increased, switching an integration time constant in each case. CONSTITUTION:The inverted input side of an operation amplifier 218 is connected to the input terminal 211 of an integrating circuit 104 through an input resistor 212. A parallel circuit consisting of an amplifying resistor 217 and integrating capacitors 213, 216 is connected between the inverted side input terminal and output terminal of an operational amplifier 218, a switch 215 is connected to an integrating capacitor 213 in series, and an integration time constant is switched by turning on/off the switch 215. The integration time constant of the integrating circuit is set up so as to sufficiently maintain the accuracy even in a low bit rate normally as a long time constant, and when the influence of fading starts to appear, the time constant is switched to a short integration time constant. Consequently, highly accurately equalization can be attained even in the case of a low bit rate and the equalizer can sufficiently follow up also the changing speed of fading.
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公开(公告)号：JPH0265423A
公开(公告)日：1990-03-06
申请号：JP21682588
申请日：1988-08-31
Applicant: TOSHIBA CORP
Inventor： TANAKA SHUICHI , WATANABE TAICHI
IPC: H04B7/08
Abstract: PURPOSE:To attain pulling-in to the in-phase state with high accuracy by retarding a fixed start timing of a phase shift quantity by a phase shift quantity fixing means by a prescribed time after a fundamental wave of a phase modulation signal does not exist in a synthesis signal. CONSTITUTION:A synthesis signal IG outputted from an in-phase power synthesizer 4 is extracted of an amplitude modulation wave AS via a synthesis signal amplifier circuit 5 and a detector 53 and the result is led to a lag/lead deciding circuit 6 and after a filter 61 of the circuit 6 extracts the fundamental wave component of the phase modulation wave CS is extracted, the result is inputted to a comparator 62. Even if entry to the in-phase state is detected, the state is not shifted to the holding control of the in-phase state at that point of time and the signal is delayed by a time equal to a delay time of a one-shot multivibrator 9 by a delay circuit 15 and the result is supplied to an up-down counter 11 to continue the variable control of the phase shift of an infinite phase shifter. Thus, even if there is a decision limit in the comparator 62, the in-phase region is made narrow and the pulling-in to the in-phase state is attained with high accuracy.
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公开(公告)号：JPH0265422A
公开(公告)日：1990-03-06
申请号：JP21682488
申请日：1988-08-31
Applicant: TOSHIBA CORP
Inventor： WATANABE TAICHI , TANAKA SHUICHI
IPC: H04B7/08
Abstract: PURPOSE:To simplify a circuit design and a circuit constitution and to miniaturize the title receiver by setting a time constant of an automatic gain control circuit to a sufficiently large value with respect to a fundamental wave frequency of a phase modulation signal and deciding the level of the gain control signal outputted from the automatic gain control circuit at a deciding circuit. CONSTITUTION:The time constant of an existing gain control circuit 52 in a synthesis signal amplifier circuit 5 is selected sufficiently longer than the frequency of the phase modulation signal CS. Then the gain control voltage GS outputted from the gain control circuit 52 is subjected to level decision by a Schmitt trigger circuit 54 to decide the opposite phase state between a main reception intermediate frequency signal IM and a sub reception intermediate frequency signal IS. Thus, a filter circuit for frequency 2fp using an active filter to decide the opposite phase state is not required. Then the circuit design and the circuit constitution are much simplified.
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公开(公告)号：JPH01200750A
公开(公告)日：1989-08-11
申请号：JP2391588
申请日：1988-02-05
Applicant: NIPPON TELEGRAPH & TELEPHONE , TOSHIBA CORP
Inventor： YOSHIKAWA TATSUO , TANAKA SHUICHI , WATANABE TAICHI
Abstract: PURPOSE:To attain a simplified and precise switching control by using the output of an identifying device and making an erroneous pulse deciding signal obtained with a logic-processing the switching control signal of a receiving system. CONSTITUTION:Two low-order bits among the outputs S1I-S4I and S1Q-S4Q of the identifying devices 15a and 15b are inputted to exclusive OR gates 31a and 31b, respectively. Next, the output of the gates 31a and 31b is inputted to an AND gate 32, an AND is taken, and an erroneous pulse deciding signal CS is outputted through a one shot multivibrator 33. Then, the signal CS is supplied to a receiving system switching circuit as a switching control signal. Thus, circuit quality can be detected stably, and a switching control whose handling is simplified and precise can be executed.
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公开(公告)号：JPS6488981A
公开(公告)日：1989-04-03
申请号：JP24401887
申请日：1987-09-30
Applicant: TOSHIBA CORP
Inventor： TANAKA SHUICHI , KAKIZAKI MIKIO
IPC: G11B27/02 , G11B27/034
Abstract: PURPOSE:To delay-control the reproduction starting of each block and to allow and user to easily execute the good reproduction by storing selected plural code data in a fifth means without being over a time limit set by a second means and reading the code data based on time difference obtained by a forth means at the time of the reproduction. CONSTITUTION:A reproducing and editing device is applied to a CD device, the operation of a key switch 11 is decoded by a key switch decoding part 12, a CD reproducing part 14 is made to be a prescribed operated state by a sequence control part 13 and a prescribed display is executed on a display 16. The reproducing part 14 reads the data contracted in a disk 17 by a pickup 18, a servocontrol part 21 processes an error signal and a signal processing part 20 processes the data. A block selection control part 27 controls a memory address control part 26 connected to a memory part 22 to which the output of the reproducing part 14 is inputted, a block length calculating part 28, a local length block selecting part 30, a rest time arithmetic calculating part 31 and a comparison arithmetic operation part 29.
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