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公开(公告)号：JPH05335973A
公开(公告)日：1993-12-17
申请号：JP16046792
申请日：1992-06-19
Applicant: TOSHIBA CORP
Inventor： KODAMA TOMOKO , NAKAMURA MAKOTO
Abstract: PURPOSE:To reduce a decoding delay time without deteriorating a decoding rate by using at least one data among data inputted newly to each shift register and selecting a survival path this time. CONSTITUTION:A branch metric calculation circuit 9 calculates a branch metric of reception signals r0, r1 received from an input terminal 8 and outputs it to an ACS circuit 10. The ACS circuit 10 selects a maximum likelihood path able to be transited to each state from the path metric calculated by the accumulation of the branch metrics. When a survival path is revised, a Viterbi decoder does not use oldest bit able to be designated when the state is transited as a bit added newly for the revision of the survival path but uses a new bit. Thus, the decoding delay time is reduced more than that of a conventional decoder. A decoding delay time is made equal to a stop length by using a bit at a location representing newest information especially in the coder among bits expressing the state of the transit destination.
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公开(公告)号：JPH02312338A
公开(公告)日：1990-12-27
申请号：JP13428089
申请日：1989-05-26
Applicant: TOSHIBA CORP
Inventor： NAKAMURA MAKOTO , BABA SHINICHI , KODAMA TOMOKO
Abstract: PURPOSE:To suppress the mean distortion of a reproducing analog signal by employing such methed to conform a signal obtained by digitizing an analog signal to a bit string representing the signal point of a multivalue modulation signal that a bit with low reproducing distorion sensitivity in a digital signal is allocated to a bit with a high mean error rate in the bit string. CONSTITUTION:An information source encoder circuit 11 inputs the analog signal 100, and outputs the digital signal 110, and a serial-parallel conversion circuit 12 converts the digital signal 110 into a two-bit parallel signal 120 at every n bits. A sequence conversion circuit 13 receives the parallel signal 120 of n bits, and performs the replacement of sequence of the bit based on a prescribed rule. In other words, as the method to respond the digital signal 110 to the bit string representing the signal point of the multivalue modulation signal, such method that the sequence of the signal is converted so as to allocate the bit with the low reproducing distortion sensitivity in the digital signal 110 to the bit with the high mean error rate in the bit string, is employed. Thereby, it is possible to keep the distortion of a reproducing analog voice signal due to a frequently generated transmission error at a low level.
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公开(公告)号：JPH0614075A
公开(公告)日：1994-01-21
申请号：JP16706092
申请日：1992-06-25
Applicant: TOSHIBA CORP
Inventor： KODAMA TOMOKO , TANAKA HIROKAZU
Abstract: PURPOSE:To obtain a transparent coding modulator with a small band expansion ratio by applying independent convolution coding to two orthogonal channels with respect to signals subject to differential logic coding, mapping the result and selecting a convolution coding ratio to be a specific range. CONSTITUTION:An input digital signal (transmission rate is R0) series is inputted to a rate converter 1, in which the signal is divided into two sets of m1+m2 series. The transmission rate of them is respectively R1, R2, and the signals m1, m2 are fed to a differential coder 2, from which signals of two sets of m1+m2 series are obtained. Then the m1 series is subject to convolution coding by coders 3, 4 with a coding ratio (r) according to equation II. The output is converted into a signal series whose transmission rate is R2 and the converted series is inputted to mapping circuits 5, 6 together with the m2 series. The mapped signals are inputted to a modulator 7, from which a modulation signal whose modulation rate is R2 is outputted. Thus, the transparent coding modulation system is realized against phase uncertainty of a recovered carrier at a lower band expansion ratio than that of a conventional system.
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公开(公告)号：JPH05235906A
公开(公告)日：1993-09-10
申请号：JP13355492
申请日：1992-05-26
Applicant: TOSHIBA CORP
Inventor： KODAMA TOMOKO , NAKAMURA MAKOTO , SAITOU TATSUNORI
Abstract: PURPOSE:To eliminate an erroneous symbol with a high probability and to enhance the error correction capability when decoding with elimination and error correction is implemented by selecting a symbol likelihood to be minimum value of m-sets of dot likelihood. CONSTITUTION:The decoder is provided with a bit likelihood calculation means calculating a bit likelihood to each of nXm bits of demodulation signals from a reception signal, a symbol likelihood calculation circuit 25 comparing m-sets of bit likelihoods corresponding to each of n-sets of symbols of a code and outputting a minimum value as the symbol likelihood, and an elimination error correction circuit 27 regarding s-sets (s is a positive integer) in the smaller order of the symbol likelihoods among n-symbols of a demodulation signal as missing symbols and implementing (s-missing and t-error correction) decoding (t is an integer being zero or over). Since the symbol likelihood is set to be minimum value of the m-sets of bit margins, the bit likelihood with least reliability in that of symbols is used for the symbol likelihood as it is, and even when even one bit with lower reliavbility is include, the symbol is used or a missing symbol.
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公开(公告)号：JPH04129448A
公开(公告)日：1992-04-30
申请号：JP25154690
申请日：1990-09-20
Applicant: TOSHIBA CORP
Inventor： TANAKA SHUICHI , NAKAMURA MAKOTO , KODAMA TOMOKO
Abstract: PURPOSE:To attain accurate frame synchronization locking at all times by implementing insertion of a frame synchronizing signal and establishment of frame synchronization before differential logic coding and after differential logic decoding respectively. CONSTITUTION:A frame insertion means 1 is arranged before a differential logic coding means 2 in a sender side equipment to insert a frame synchronizing signal to a transmission digital signal before differential logic coding, and a frame synchronization means 10 is arranged after a differential logic decoding means 9 at a receiver side equipment to implement the processing for establishing frame synchronization. Then a signal selection means 8 is provided between an error correction decoding means 6 and the differential logic decoding means 9, and a reception digital signal not implementing error correction decoding is selected when the frame synchronization is not established and the reception digital signal after error correction decoding is selected while the frame synchronization is established to implement the differential logic decoding processing. Thus, frame synchronization is accurately taken.
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Patent Agency Ranking
公开(公告)号：JPH02288752A
公开(公告)日：1990-11-28
申请号：JP11162289
申请日：1989-04-28
Applicant: TOSHIBA CORP
Inventor： KODAMA TOMOKO , NAKAMURA MAKOTO
IPC: H04L27/34
Abstract: PURPOSE:To constitute a transparent error correction coding to phase rotation by applying error correction coding independently to sets of each series relating to the decision of a quadrant of a phase plane and other series among m sets of series deciding the arrangement of signal points. CONSTITUTION:Eight sets of digital signal series are inputted from input terminals 1-1-1-8. Two bits inputted from the two input terminals 1-1, 1-2 are fed to a differential logic circuit 2 and the two bits being the result of additive operation are fed to same coders 3, 4 respectively, where they are coded. On the other hand, 8 bits inputted from remaining input terminals 1-3-1-8 are fed to a coder 5, where they are coded, Thus, error correction coding is applied independently to sets of each series relating to the decision of the quadrant of the phase plane and other series to realize the transparent coding to the phase rotation.
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公开(公告)号：JPH0583318A
公开(公告)日：1993-04-02
申请号：JP23801791
申请日：1991-09-18
Applicant: TOSHIBA CORP
Inventor： TANAKA HIROKAZU , KODAMA TOMOKO
Abstract: PURPOSE:To suppress the deterioration in a signal component at a high frequency even when a nonlinear amplifier is in use by consisting the system so that a signal point locus does not pass the origin on a phase amplitude plane. CONSTITUTION:A serial parallel converter 1 converts a serial input signal into a parallel signal, a logic circuit 2 converts a 4-value signal into a ternary signal and a differential logic circuit 4 takes a difference of the ternary signals. Then A QAM(quadrature amplitude modulation) modulator 3 modulates the signal. That is, when a signal point transits on the phase amplitude plane in the QAM system, the point is transited by applying a limit partly so that no transition is caused to the signal point on a quadrant symmetrical to the origin. Or the signal is transited with a limit to signal point transition by a prescribed number so that the locus of the signal point passes around the origin to prevent the signal point does not pass through the origin. Thus, a fluctuation of an envelope amplitude is less even after passing through a band limit filter and the deterioration in the characteristic of the signal component at a high frequency is suppressed even with the use of a nonlinear amplifier.
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公开(公告)号：JPH0344217A
公开(公告)日：1991-02-26
申请号：JP18077589
申请日：1989-07-12
Applicant: TOSHIBA CORP
Inventor： KODAMA TOMOKO , NAKAMURA MAKOTO
IPC: H03M13/00
Abstract: PURPOSE:To attain the decoding of an error correction code with only the addition of a simple circuit by providing a threshold level decision means deciding whether or not the weight of a residue series calculated from a reception signal series is less than a threshold level. CONSTITUTION:The device is provided with a signal input means 101 inputting a reception signal series, a signal storage means 102 storing the reception signal series inputted from the signal input means 101, a residue calculation means 103 calculating a residue series from the reception signal series, and a threshold level decision means 104 deciding whether or not the weight of the residue series is the threshold level or below. Moreover, the device is provided with a pattern detection means 105 detecting whether or not the residue series calculated by the residue calculation means 103 is coincident with a preset prescribed pattern, an error correction means 106 correcting an error of a stored reception signal series by the signal storage means 102 based on the result of detection and a signal output means 107. Thus, the decoding of the error correction code is attained by having only to add a simple circuit.
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公开(公告)号：JPH02311034A
公开(公告)日：1990-12-26
申请号：JP13162189
申请日：1989-05-26
Applicant: TOSHIBA CORP
Inventor： KODAMA TOMOKO , NAKAMURA MAKOTO
Abstract: PURPOSE:To increase the coding rate of an error correction circuit, to shorten the decoding delay time and to increase the degree of freedom of coding by using an error correction circuit by a BCH code as a block code in the inside of a differential logic circuit. CONSTITUTION:A digital signal series is inputted from an input terminal 101 at a transmission side and fed to a differential logic coding circuit 102. The circuit applies additive operation to the series and the series obtained as the result is fed to a BCH coding circuit 103. The circuit 103 applies coding with binary BCH code and the result is fed to a BPSK modulator 104. However, the generation polynomial of the BCH code does not have 1 as its root. The modulator 104 outputs a BPSK modulation signal to a channel S and transmitted to a reception side BPSK demodulator 105. Then decoding and differential operation are applied via the BCH decoding circuit 106 and a differential logic decoding circuit 107 and the result is outputted from an output terminal 108. Thus, the coding rate of the error correction circuit is increased to increase the degree of freedom of coding and the decoding delay time is shortened.
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公开(公告)号：JPH02303221A
公开(公告)日：1990-12-17
申请号：JP12361489
申请日：1989-05-17
Applicant: TOSHIBA CORP
Inventor： MORII MASAKATSU , KASAHARA MASAO , KODAMA TOMOKO , NAKAMURA MAKOTO
Abstract: PURPOSE:To quicken the decoding processing by varying a series of decoding procedures obtaining an error location polynomial and an error numeral polynomial from a residue polynomial in various kinds of ways. CONSTITUTION:A reception symbol R(X) is inputted from an input terminal 1 and supplied to a residue calculation circuit 2 and a storage circuit 3. A fundamental equation arithmetic circuit 4 receives a residue obtained from the residue calculation circuit 2 to obtain coefficients of two polynomials W(X), N(X). The coefficient of the equation W(X) calculated by the fundamental equation arithmetic circuit 4 is fed to an error location calculation circuit 5. When a reed Solomon code is generated by a generation polynomial, number of data stored in a storage circuit 10 is decreased. An error correction circuit 7 corrects an error of reception series to given an output to an output terminal 8.
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