公开(公告)号：US08519494B2

公开(公告)日：2013-08-27

申请号：US12737037

申请日：2009-04-21

Applicant: Torsten Kramer ,  Marcus Ahles ,  Armin Grundmann ,  Kathrin Knese ,  Hubert Benzel ,  Gregor Schuermann ,  Simon Armbruster

Inventor： Torsten Kramer ,  Marcus Ahles ,  Armin Grundmann ,  Kathrin Knese ,  Hubert Benzel ,  Gregor Schuermann ,  Simon Armbruster

IPC: G01P15/08

CPC classification number: B81C1/00158 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81C2201/0115 ,  B81C2201/0136 ,  G01L9/0042

Abstract: A method for manufacturing a micromechanical diaphragm structure having access from the rear of the substrate includes: n-doping at least one contiguous lattice-type area of a p-doped silicon substrate surface; porously etching a substrate area beneath the n-doped lattice structure; producing a cavity in this substrate area beneath the n-doped lattice structure; growing a first monocrystalline silicon epitaxial layer on the n-doped lattice structure; at least one opening in the n-doped lattice structure being dimensioned in such a way that it is not closed by the growing first epitaxial layer but instead forms an access opening to the cavity; an oxide layer being created on the cavity wall; a rear access to the cavity being created, the oxide layer on the cavity wall acting as an etch stop layer; and the oxide layer being removed in the area of the cavity.

Abstract translation: 用于制造从衬底的后部进入的微机械膜结构的方法包括：n掺杂p掺杂硅衬底表面的至少一个连续的格子型区域; 在n掺杂的晶格结构下面蚀刻衬底区域; 在该n型掺杂晶格结构下面的该衬底区域中产生空腔; 在n掺杂晶格结构上生长第一单晶硅外延层; n掺杂晶格结构中的至少一个开口的尺寸设计成使得其不被生长的第一外延层闭合​​，而是形成到腔的通路口; 在空腔壁上形成氧化物层; 产生到空腔的后部通路，空腔壁上的氧化层用作蚀刻停止层; 并且在空腔的区域中去除氧化物层。

公开(公告)号：US20060271762A1

公开(公告)日：2006-11-30

申请号：US10560572

申请日：2004-06-04

Applicant: Torsten Kramer

Inventor： Torsten Kramer

IPC: G06F12/00

CPC classification number: G06F9/342 ,  G06F12/0623

Abstract: In order to provide a microcontroller and an addressing method which are distinguished by a lower storage requirement and a higher execution speed than previously known when addressing N-bit address spaces, the address length N of the N-bit address word being greater than the address length of a standard set of instruction or of equivalents of other sets of instructions of the microcontroller, it is provided that the microcontroller (10) has at least one status bit (12) by means of which a writing and/or reading of N-bit address words by at least one standard instruction of the microcontroller (10) can be forced, and the at least one status bit (12) of a microcontroller (10) is set and as a a result a writing and/or reading of N-bit address words by means of at least one standard instruction of the microcontroller (10) is forced.

Abstract translation: 为了提供一个微控制器和寻址方法，它们通过比寻址N位地址空间时先前已知的更低的存储要求和更高的执行速度来区分，N位地址字的地址长度N大于地址 微控制器的标准指令集或其他指令集的等效指令的长度，微控制器（10）具有至少一个状态位（12），通过该状态位的写入和/或读取， 可以强制微控制器（10）的至少一个标准指令的位地址字，并且设置微控制器（10）的至少一个状态位（12），并且作为结果写入和/或读取N- 通过微控制器（10）的至少一个标准指令来强制位地址字。

公开(公告)号：US06827278B1

公开(公告)日：2004-12-07

申请号：US09555306

申请日：2000-10-06

Applicant: Volker Timm ,  Ralf Malzahn ,  Wolfgang Eber ,  Dominik Berger ,  Jozef Laurentius Wilhelmus Kessels ,  Torsten Kramer

Inventor： Volker Timm ,  Ralf Malzahn ,  Wolfgang Eber ,  Dominik Berger ,  Jozef Laurentius Wilhelmus Kessels ,  Torsten Kramer

IPC: G06K1906

CPC classification number: G06K19/07769 ,  G06K19/07 ,  G06K19/0701 ,  G06K19/073

Abstract: A data carrier is disclosed. The data carrier includes a data processing unit and at least one contactless interface via which the data processing unit can be coupled to a read/write apparatus in order to exchange data signals and to take up electrical energy for the operation of the data processing unit; the data processing unit is constructed at least mainly while using at least substantially asynchronously operating logic components (asynchronous logic). The data carrier according to the invention, such as a chip card, makes optimum use of the energy applied thereto and is at the same time protected against the tapping of the signal processing steps to be executed therein.

Abstract translation: 公开了数据载体。 数据载体包括数据处理单元和至少一个非接触式接口，通过该接口，数据处理单元可耦合到读/写设备，以便交换数据信号并占用用于数据处理单元操作的电能; 数据处理单元至少主要构造在使用至少基本上异步操作的逻辑组件（异步逻辑）的同时。 根据本发明的数据载体，例如芯片卡，可以最佳地利用施加到其上的能量，同时可以防止在其中执行的信号处理步骤的窃听。

公开(公告)号：US08470631B2

公开(公告)日：2013-06-25

申请号：US12727978

申请日：2010-03-19

Applicant: Torsten Kramer ,  Kathrin Knese ,  Hubert Benzel ,  Karl-Heinz Kraft ,  Simon Armbruster

Inventor： Torsten Kramer ,  Kathrin Knese ,  Hubert Benzel ,  Karl-Heinz Kraft ,  Simon Armbruster

IPC: H01L21/00

CPC classification number: B81C1/00333 ,  B81C2201/0192 ,  B81C2203/0118 ,  B81C2203/0127 ,  H01L2924/16235

Abstract: A simple and economical method for manufacturing very thin capped MEMS components. In the method, a large number of MEMS units are produced on a component wafer. A capping wafer is then mounted on the component wafer, so that each MEMS unit is provided with a capping structure. Finally, the MEMS units capped in this way are separated to form MEMS components. A diaphragm layer is formed in a surface of the capping wafer by using a surface micromechanical method to produce at least one cavern underneath the diaphragm layer, support points being formed that connect the diaphragm layer to the substrate underneath the cavern. The capping wafer structured in this way is mounted on the component wafer in flip chip technology, so that the MEMS units of the component wafer are capped by the diaphragm layer. The support points are then cut through in order to remove the substrate.

Abstract translation: 一种用于制造非常薄的封装的MEMS部件的简单而经济的方法。 在该方法中，在部件晶片上产生大量的MEMS单元。 然后将封盖晶片安装在元件晶片上，使得每个MEMS单元设置有封盖结构。 最后，以这种方式封盖的MEMS单元被分离以形成MEMS部件。 通过使用表面微机械方法在覆盖晶片的表面中形成隔膜层，以在隔膜层下面产生至少一个洞穴，形成将隔膜层连接到洞穴下方的基底的支撑点。 以这种方式构造的封盖晶片以倒装芯片技术安装在元件晶片上，使得元件晶片的MEMS单元被隔膜层封盖。 然后将支撑点切开以去除基底。

公开(公告)号：US20110169107A1

公开(公告)日：2011-07-14

申请号：US13054435

申请日：2009-06-09

Applicant: Torsten Kramer ,  Stefan Pinter ,  Hubert Benzel ,  Matthias Illing ,  Frieder Haag ,  Simon Armbruster

Inventor： Torsten Kramer ,  Stefan Pinter ,  Hubert Benzel ,  Matthias Illing ,  Frieder Haag ,  Simon Armbruster

IPC: H01L29/84 ,  H01L21/62

CPC classification number: B81C99/008 ,  B81B7/0006 ,  B81B2207/093

Abstract: A process for manufacturing a component is described. In a first manufacturing step a base structure having a substrate, a diaphragm, and a cavern region is provided. The diaphragm is oriented substantially parallel to a main plane of extension of the substrate. The cavern region is situated between the substrate and the diaphragm, and has an access opening. In a second manufacturing step, a first conductive layer is provided at least partially in the cavern region, in particular on a second side of the diaphragm facing the substrate, perpendicularly to the main plane of extension.

Abstract translation: 描述了用于制造部件的工艺。 在第一制造步骤中，提供具有基底，隔膜和洞穴区域的基底结构。 隔膜取向为基本平行于基板延伸的主平面。 洞穴区域位于基板和隔膜之间，并且具有进入开口。 在第二制造步骤中，第一导电层至少部分地设置在垂直于主延伸平面的洞穴区域中，特别是在面向衬底的隔膜的第二侧上。