公开(公告)号：US20190229202A1

公开(公告)日：2019-07-25

申请号：US16254397

申请日：2019-01-22

Applicant: United Microelectronics Corp.

Inventor： Chun-Liang Kuo ,  Tsang-Hsuan Wang ,  Yu-Ming Hsu ,  Tsung-Mu Yang ,  Ching-I Li

IPC: H01L29/66 ,  H01L27/11 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/24 ,  H01L29/16 ,  H01L29/08 ,  H01L27/088

Abstract: A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2−L1)/L1 is equal to or less than about 1%.

公开(公告)号：US10263096B1

公开(公告)日：2019-04-16

申请号：US15878836

申请日：2018-01-24

Applicant: United Microelectronics Corp.

Inventor： Chun-Liang Kuo ,  Tsang-Hsuan Wang ,  Yu-Ming Hsu ,  Tsung-Mu Yang ,  Ching-I Li

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L27/11 ,  H01L27/088 ,  H01L29/08 ,  H01L29/16 ,  H01L29/24 ,  H01L21/8234 ,  H01L21/311

Abstract: A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2−L1)/L1 is equal to or less than about 1%.

公开(公告)号：US20220140080A1

公开(公告)日：2022-05-05

申请号：US17580622

申请日：2022-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

公开(公告)号：US20200235208A1

公开(公告)日：2020-07-23

申请号：US16836953

申请日：2020-04-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.

公开(公告)号：US10468502B2

公开(公告)日：2019-11-05

申请号：US16254397

申请日：2019-01-22

Applicant: United Microelectronics Corp.

Inventor： Chun-Liang Kuo ,  Tsang-Hsuan Wang ,  Yu-Ming Hsu ,  Tsung-Mu Yang ,  Ching-I Li

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/24 ,  H01L29/16 ,  H01L29/08 ,  H01L27/088 ,  H01L27/11

Abstract: A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2−L1)/L1 is equal to or less than about 1%.

公开(公告)号：US20190067477A1

公开(公告)日：2019-02-28

申请号：US15688824

申请日：2017-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Ming-Shiou Hsieh ,  Rong-Sin Lin ,  Han-Ting Yen ,  Tsai-Yu Wen ,  Ching-I Li

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

Abstract: A semiconductor structure includes a substrate, fin-shaped structures disposed on the substrate, an isolation layer disposed between the fin-shaped structures, and a doped region disposed in an upper portion of the isolation layer, where the doped region is doped with helium or neon.

公开(公告)号：US20130337622A1

公开(公告)日：2013-12-19

申请号：US13971763

申请日：2013-08-20

Applicant: United Microelectronics Corp.

Inventor： Chan-Lon Yang ,  Ching-Nan Hwang ,  Chi-Heng Lin ,  Chun-Yao Yang ,  Ger-Pin Lin ,  Ching-I Li

IPC: H01L49/02

CPC classification number: H01L28/24 ,  H01L21/26593 ,  H01L21/32155 ,  H01L21/76224 ,  H01L27/0629 ,  H01L28/20

Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.

Abstract translation: 提供半导体工艺，包括以下步骤。 在基板上形成多晶硅层。 对多晶硅层进行不对称双面加热处理，其中用于正面加热的功率不同于用于背面加热的功率。