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公开(公告)号：US09313017B1
公开(公告)日：2016-04-12
申请号：US14737330
申请日：2015-06-11
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Geoffrey Zhang , Hongtao Zhang , Zhaoyin D. Wu , Kun-Yung Chang
CPC classification number: H04L7/0087 , H04L7/0025 , H04L7/0062 , H04L25/03
Abstract: In an example, a clock data recovery (CDR) circuit for a receiver includes a timing error detector circuit, a loop filter, and a phase interpolator. The timing error detector circuit is coupled to receive, at a baud-rate, data samples and error samples for symbols received by the receiver. The timing error detector circuit is operable to generate both a timing error value and an estimated waveform value per symbol based on the data samples and the error samples. The loop filter is coupled to the timing error detector to receive timing error values. The phase interpolator is coupled to the loop filter to receive filtered timing error values, the phase interpolator operable to generate a control signal to adjust a sampling phase used to generate the data samples and the error samples.
Abstract translation: 在一个示例中，用于接收机的时钟数据恢复（CDR）电路包括定时误差检测器电路，环路滤波器和相位内插器。 定时误差检测器电路被耦合以以波特率接收由接收器接收的符号的数据样本和误差样本。 定时误差检测器电路可操作以基于数据样本和误差样本同时产生每个符号的定时误差值和估计波形值。 环路滤波器耦合到定时误差检测器以接收定时误差值。 相位内插器耦合到环路滤波器以接收滤波的定时误差值，相位插值器可操作以产生控制信号以调整用于生成数据样本和误差采样的采样相位。
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公开(公告)号：US09237047B1
公开(公告)日：2016-01-12
申请号：US14689294
申请日：2015-04-17
Applicant: Xilinx, Inc.
Inventor： Hongtao Zhang , Geoffrey Zhang , Patrick Satarzadeh , Zhaoyin D. Wu
CPC classification number: H04L27/06 , H04L25/061
Abstract: A circuit for receiving data in an integrated circuit is described. The circuit comprises a receiver configured to receive an input signal and to generate output data based upon the input signal, the receiver having a level detection circuit coupled to receive the input signal; and a calibration circuit coupled to the receiver, the calibration circuit having an input for receiving the input signal; an error detection circuit coupled to the input, the error detection circuit coupled to receive the input signal, a first reference voltage and a second reference voltage; and a control circuit coupled to an output of the error detection circuit, wherein the control circuit selectively generates either an offset control signal or an amplitude control signal based upon comparisons of the input signal to the first reference voltage and the second reference voltage. A method of receiving data is also disclosed.
Abstract translation: 描述了用于在集成电路中接收数据的电路。 该电路包括接收器，配置为接收输入信号并基于输入信号产生输出数据，接收器具有耦合以接收输入信号的电平检测电路; 以及校准电路，其耦合到所述接收器，所述校准电路具有用于接收所述输入信号的输入; 耦合到所述输入端的误差检测电路，所述误差检测电路被耦合以接收所述输入信号，第一参考电压和第二参考电压; 以及耦合到所述误差检测电路的输出的控制电路，其中所述控制电路基于所述输入信号与所述第一参考电压和所述第二参考电压的比较来选择性地产生偏移控制信号或幅度控制信号。 还公开了接收数据的方法。
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13.发明授权公开(公告)号：US11038768B1
公开(公告)日：2021-06-15
申请号：US15267002
申请日：2016-09-15
Applicant: Xilinx, Inc.
Inventor： Ivan O. Madrigal , Michael O. Jenkins , Hong S. Ahn , Murtuza Z. Cutleriwala , Alan C. Wong , Christopher J. Borrelli , Yohan Frans , Geoffrey Zhang , Hongtao Zhang
IPC: H04L25/03 , H04L12/24 , G06F30/331
Abstract: A method relates generally to comparison of a communications system modelled with a behavioral model and implemented with a circuit realization. In this method, operation of the communications system is simulated with the behavioral model on a computing device to obtain a first pulse response. The simulating includes first equalizing first data with a first equalizer of the behavioral model to obtain the first pulse response. The circuit realization is operated to obtain a second pulse response. The operating includes: second equalizing second data corresponding to the first data with a second equalizer of the circuit realization to obtain the second pulse response. The second pulse response from the circuit realization is loaded to memory of the computing device. The first pulse is loaded to the memory of the computing device. The first pulse response and the second pulse response are compared with one another by the computing device.
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公开(公告)号：US10224937B1
公开(公告)日：2019-03-05
申请号：US15959104
申请日：2018-04-20
Applicant: Xilinx, Inc.
Inventor： Zhaoyin D. Wu , Geoffrey Zhang , Parag Upadhyaya , Kun-Yung Chang
Abstract: An example clock and data recovery (CDR) circuit includes a phase interpolator, a fractional-N phase locked loop (PLL) configured to supply a clock signal to the phase interpolator, and a phase detector configured to generate a phase detect result signal in response to phase detection of data samples and crossing samples of a received signal, the data samples and the crossing samples being generated based on a data phase and a crossing phase, respectively, or a sampling clock supplied by a phase interpolator. The CDR circuit further includes a digital loop filter configured to generate a phase interpolator code for controlling the phase interpolator, the digital loop filter including a phase path and a frequency path. The CDR circuit further includes a control circuit configured to control the digital loop filter to disconnect the frequency path from the phase path and to connect the frequency path to a control input of the fractional-N PLL.
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公开(公告)号：US20180287837A1
公开(公告)日：2018-10-04
申请号：US15471364
申请日：2017-03-28
Applicant: Xilinx, Inc.
Inventor： Hongtao Zhang , Yohan Frans , Geoffrey Zhang
CPC classification number: H04L27/01 , H03M1/182 , H03M1/361 , H04B1/06 , H04B2203/5425 , H04L25/063 , H04Q2213/03
Abstract: A receiver includes: an automatic gain controller (AGC) configured to receive an analog signal; an analog-to-digital converter (ADC) configured to receive an output from the AGC and to output a digitized signal, wherein a most significant bit of the digitized signal corresponds to a sliced data, and a least significant bit of the digitized signal corresponds to an error signal; and an adaptation unit configured to control the AGC, the ADC, or both the AGC and the ADC, based at least in part on the digitized signal to achieve a desired data digitization and data slicing.
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Patent Agency Ranking
公开(公告)号：US09276782B1
公开(公告)日：2016-03-01
申请号：US14698588
申请日：2015-04-28
Applicant: Xilinx, Inc.
Inventor： Hongtao Zhang , Geoffrey Zhang , Yu Liao
IPC: H04L25/03
CPC classification number: H04L25/03146 , H04L25/03057
Abstract: In a receiver, there is a precursor iterative canceller (“PIC”) having first and second paths. A postcursor decision block is coupled to the PIC to provide a decision signal thereto. The PIC includes: comparators for receiving an input signal and corresponding threshold inputs for precursor ISI speculation; and select circuits for selecting a first speculative input for the first path and a second speculative input for the second path, respectively associated with a negative precursor contribution and a positive precursor contribution. The first path and the second path in combination include at least a first stage and a second stage for processing the first speculative input and the second speculative input. The decision signal is provided to the first stage and to the select circuits. The select circuits are coupled to receive the decision signal for selection of the first speculative input and the second speculative input.
Abstract translation: 在接收机中，存在具有第一和第二路径的前体迭代消除器（“PIC”）。 后端决策块被耦合到PIC以向其提供判决信号。 PIC包括：用于接收输入信号的比较器和用于前体ISI投机的相应阈值输入; 以及选择用于选择第一路径的第一推测输入和用于第二路径的第二推测输入，分别与负前驱贡献和正前驱贡献相关联。 组合的第一路径和第二路径包括用于处理第一推测输入和第二推测输入的至少第一级和第二级。 决定信号被提供给第一级和选择电路。 选择电路被耦合以接收用于选择第一推测输入和第二推测输入的判定信号。
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公开(公告)号：US11522735B1
公开(公告)日：2022-12-06
申请号：US16998864
申请日：2020-08-20
Applicant: Xilinx, Inc.
Inventor： Kevin Zheng , Hongtao Zhang , Geoffrey Zhang
Abstract: Apparatus and associated methods relate to an ADC-based digital receiver including a feedforward equalizer (FFE) that has m precursor taps and n postcursor taps to equalize the precursor portion, and to adapt postcursor intersymbol interference (ISI) through a predetermined equalization coefficient selected to counteract the noise boosting effect associated with the precursor equalization. In an illustrative example, the receiver may dynamically balance noise and ISI through adaptively determining a coefficient hp1 of a first postcursor tap of a first FFE and a coefficient h1 of a first postcursor tap of a second equalizer adapted to substantially reduce or eliminate additional ISI introduced by the first FFE. The first FFE may optimize ISI removal and noise reduction, for example. One of the coefficients h1 and hp1 may be predetermined, and then the other coefficient may be iteratively adapted to trade off precursor ISI and postcursor ISI to minimize BER.
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公开(公告)号：US11423303B1
公开(公告)日：2022-08-23
申请号：US16691399
申请日：2019-11-21
Applicant: Xilinx, Inc.
Inventor： Shuo Jiao , Romi Mayder , Bowen Li , Geoffrey Zhang
Abstract: Apparatus and associated methods relate to providing a machine learning methodology that uses the machine learning's own failure experiences to optimize future solution search and provide self-guided information (e.g., the dependency and independency among various adaptation behavior) to predict a receiver's equalization adaptations. In an illustrative example, a method may include performing a first training on a first neural network model and determining whether all of the equalization parameters are tracked. If not all of the equalization parameters are tracked under the first training, then, a second training on a cascaded model may be performed. The cascaded model may include the first neural network model, and training data of the second training may include successful learning experiences and data of the first neural network model. The prediction accuracy of the trained model may be advantageously kept while having a low demand for training data.
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公开(公告)号：US10530561B1
公开(公告)日：2020-01-07
申请号：US16359921
申请日：2019-03-20
Applicant: Xilinx, Inc.
Inventor： Zao Liu , Yang Liu , Zhaoyin D. Wu , Geoffrey Zhang , Yu Xu , Alan C. Wong
Abstract: Apparatus and associated methods relate to using a high learning rate to speed up the training of a receiver and switching from a high learning rate to a low learning rate for fine tuning based on exponentially weighted moving average convergence. In an illustrative example, a selection circuit may switch the high learning rate to the low learning rate based on a comparison of a moving average difference en to a predetermined stability criteria T1 of the receiver. The moving average difference en may include an exponentially weighted moving average of a difference between two consecutive exponentially weighted moving averages of an operation parameter un of the signal communication channel. By using this method, the training time for the receiver may be advantageously reduced.
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公开(公告)号：US10404408B1
公开(公告)日：2019-09-03
申请号：US15377780
申请日：2016-12-13
Applicant: Xilinx, Inc.
Inventor： Winson Lin , Hongtao Zhang , Yu Xu , Geoffrey Zhang
Abstract: An example method of capturing an error distribution data for a serial channel includes: receiving a signal from the serial channel at a receiver in an integrated circuit (IC), the signal encoding data using pulse amplitude modulation (PAM) scheme having more than two levels; determining a plurality of symbols from the signal, each of the plurality of symbols encoding a plurality of bits; comparing the plurality of symbols with a plurality of expected symbols to detect a plurality of symbol errors; generating the error distribution data by accumulating numbers of the plurality of symbol errors across a plurality of bins based error type; and transmitting the error distribution data from the receiver to a computing system for processing.
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