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    SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
    11.
    发明申请
    SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF 有权
    半导体结构及其制造方法

    公开(公告)号：US20170029272A1

    公开(公告)日：2017-02-02

    申请号：US15222006

    申请日：2016-07-28

    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation

    Inventor： PENG REN

    IPC: B81C1/00 ,  H01L23/00 ,  H01L21/67 ,  H01L21/687 ,  H01L23/48 ,  H01L21/768

    CPC classification number: B81C1/00801 ,  B81C2201/0154 ,  B81C2201/05 ,  B81C2203/0778 ,  H01L21/67063 ,  H01L21/6715 ,  H01L21/687 ,  H01L21/76861 ,  H01L21/76873 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02317 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/13024

    Abstract: A method for fabricating a semiconductor structure includes providing a substrate with a first surface and a second surface, wherein at least one soldering pad is formed on the first surface of the substrate. The method also includes forming at least one via to expose each soldering pad by etching the substrate from the second surface, forming a seed layer to cover the second surface of the substrate and the sidewall and the bottom surfaces of each via, and then forming a redistribution metal layer over a portion of the seed layer formed on the sidewall and the bottom surfaces of each via and the second surface of the substrate surrounding each via. The method further includes alternately performing a pre-wetting process and a chemical etching process to completely remove the portion of the seed layer not covered by the redistribution metal layer.

    Abstract translation: 一种制造半导体结构的方法包括：提供具有第一表面和第二表面的基底，其中在所述基底的第一表面上形成至少一个焊盘。 该方法还包括形成至少一个通孔以通过从第二表面蚀刻衬底来暴露每个焊盘，形成晶种层以覆盖衬底的第二表面和每个通孔的侧壁和底表面，然后形成 再分布金属层在形成在每个通孔的侧壁和底表面上的种子层的一部分上，以及围绕每个通孔的基板的第二表面。 该方法还包括交替地执行预润湿处理和化学蚀刻工艺以完全去除未被再分布金属层覆盖的种子层的部分。

    Methods and Structures of Integrated MEMS-CMOS Devices
    12.
    发明申请
    Methods and Structures of Integrated MEMS-CMOS Devices 有权
    集成MEMS-CMOS器件的方法和结构

    公开(公告)号：US20160176708A1

    公开(公告)日：2016-06-23

    申请号：US14985388

    申请日：2015-12-30

    Applicant: mCube, Inc.

    Inventor： Sudheer S. Sridharamurthy ,  Te-Hse Terrence Lee ,  Ali J. Rastegar ,  Mugurel Stancu ,  Xiao Charles Yang

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/00801 ,  B81B3/0013 ,  B81B3/0086 ,  B81B7/0022 ,  B81B7/0064 ,  B81B2203/0163 ,  B81B2207/094 ,  B81C1/00238 ,  B81C2201/0132 ,  B81C2201/05 ,  B81C2203/0735 ,  H01L27/0688

    Abstract: A method for fabricating an integrated MEMS-CMOS device uses a micro-fabrication process that realizes moving mechanical structures (MEMS) on top of a conventional CMOS structure by bonding a mechanical structural wafer on top of the CMOS and etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE). During etching of the mechanical layer, CMOS devices that are directly connected to the mechanical layer are exposed to plasma. This sometimes causes permanent damage to CMOS circuits and is termed Plasma Induced Damage (PID). Embodiments of the present invention presents methods and structures to prevent or reduce this PID and protect the underlying CMOS circuits by grounding and providing an alternate path for the CMOS circuits until the MEMS layer is completely etched.

    Abstract translation: 一种用于制造集成的MEMS-CMOS器件的方法使用微型制造工艺，其通过在CMOS的顶部上结合机械结构晶片并使用等离子体蚀刻来蚀刻机械层来实现在常规CMOS结构之上的移动机械结构（MEMS） 工艺，如深层反应离子蚀刻（DRIE）。 在蚀刻机械层期间，直接连接到机械层的CMOS器件暴露于等离子体。 这有时会导致对CMOS电路的永久性损坏，称为等离子体诱发损伤（PID）。 本发明的实施例提出了防止或减少该PID并且通过接地并为CMOS电路提供替代路径来保护下面的CMOS电路直到MEMS层被完全蚀刻的方法和结构。

    METHODS AND STRUCTURES OF INTEGRATED MEMS-CMOS DEVICES
    15.
    发明申请
    METHODS AND STRUCTURES OF INTEGRATED MEMS-CMOS DEVICES 有权
    集成MEMS-CMOS器件的方法和结构

    公开(公告)号：US20130236988A1

    公开(公告)日：2013-09-12

    申请号：US13788503

    申请日：2013-03-07

    Applicant: MCUBE, INC.

    Inventor： Sudheer S. Sridharamurthy ,  Te-Hse Terrence Lee ,  Ali J. Rastegar ,  Mugurel Stancu ,  Xiao Charles Yang

    IPC: H01L29/66

    CPC classification number: B81C1/00801 ,  B81B3/0013 ,  B81B3/0086 ,  B81B7/0022 ,  B81B7/0064 ,  B81B2203/0163 ,  B81B2207/094 ,  B81C1/00238 ,  B81C2201/0132 ,  B81C2201/05 ,  B81C2203/0735 ,  H01L27/0688

    Abstract: A method for fabricating an integrated MEMS-CMOS device uses a micro-fabrication process that realizes moving mechanical structures (MEMS) on top of a conventional CMOS structure by bonding a mechanical structural wafer on top of the CMOS and etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE). During etching of the mechanical layer, CMOS devices that are directly connected to the mechanical layer are exposed to plasma. This sometimes causes permanent damage to CMOS circuits and is termed Plasma Induced Damage (PID). Embodiments of the present invention presents methods and structures to prevent or reduce this PID and protect the underlying CMOS circuits by grounding and providing an alternate path for the CMOS circuits until the MEMS layer is completely etched.

    Abstract translation: 一种用于制造集成的MEMS-CMOS器件的方法使用微型制造工艺，其通过在CMOS的顶部上结合机械结构晶片并使用等离子体蚀刻来蚀刻机械层来实现在常规CMOS结构之上的移动机械结构（MEMS） 工艺，如深层反应离子蚀刻（DRIE）。 在蚀刻机械层期间，直接连接到机械层的CMOS器件暴露于等离子体。 这有时会导致对CMOS电路的永久性损坏，称为等离子体诱发损伤（PID）。 本发明的实施例提出了防止或减少该PID并且通过接地并为CMOS电路提供替代路径来保护下面的CMOS电路直到MEMS层被完全蚀刻的方法和结构。

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