公开(公告)号：EP2590107B1

公开(公告)日：2019-08-21

申请号：EP11306417.4

申请日：2011-11-03

Applicant: STMicroelectronics Application GmbH

Inventor： Boehler, Juergen

IPC: G06K7/00

公开(公告)号：EP3401826A2

公开(公告)日：2018-11-14

申请号：EP18171148.2

申请日：2018-05-08

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： COLOMBO, Roberto ,  GROSSIER, Nicolas Bernard ,  DI SIRIO, Giovanni ,  RE FIORENTIN, Lorenzo

IPC: G06F21/57 ,  G06F21/60 ,  G06F21/77 ,  H03K19/177

CPC classification number: G06F21/71 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/0772 ,  G06F21/57 ,  G06F21/602 ,  G06F21/72 ,  G06F21/77 ,  H03K19/17728 ,  H04L9/0618 ,  H04L2209/12 ,  H04L2209/127

Abstract: A hardware secure element is described. The hardware secure element comprises a microprocessor (106a) and a memory (108), such as a non-volatile memory, having stored a plurality of software routines (HI, H2) executable by the microprocessor (106a), wherein each software routine (HI, H2) starts at a respective memory start address. The hardware secure element comprises also a receiver circuit configured to receive data comprising a command (CMD), and a hardware message handler module (316). The hardware message handler module (316) determines a software routine (HI, H2) to be executed by the microprocessor (106a) as a function of the command (CMD), and provides data (ADDR) to the microprocessor (106a) indicating the software routine to be executed.

公开(公告)号：EP2690839B1

公开(公告)日：2018-09-26

申请号：EP12305895.0

申请日：2012-07-23

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics Application GmbH

Inventor： Boehler, Juergen ,  Charles, Alexandre

IPC: H04W4/80 ,  H04W12/02 ,  H04L29/06 ,  H04M1/725 ,  H04W4/00 ,  H04B5/00

CPC classification number: H04B5/0056 ,  H04L63/0492 ,  H04M1/7253 ,  H04M2250/04 ,  H04W4/80 ,  H04W12/02

Abstract: The NFC apparatus comprises a first controller interface (MINT1) and a second controller interface (MINT2), a first communication channel (LK1) coupled to said first controller interface, a second communication channel (LK2) connected to said second controller interface, a secure element (SE) including a secure element interface connected to said first communication channel, encryption/decryption means (CRL) configured to encrypt data to be sent on said first communication channel for being framing into said encrypted frames and to decrypt encrypted data extracted from said encrypted frames and received from said first communication channel, management means (MMG) configured to control said encryption/decryption means for managing the encrypted communication with said NFC controller, a device host (DH) including a host device interface coupled to said second controller interface and control means (CRTM) configured to control said management means through non encrypted commands exchanged on said first and second communication channels.

公开(公告)号：EP4296850A1

公开(公告)日：2023-12-27

申请号：EP23176646.0

申请日：2023-06-01

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V.

Inventor： ZARGAR, Asif Rashid ,  COLOMBO, Roberto

IPC: G06F9/4401

Abstract: A processing system (10a) is disclosed. When the processing system (10a) is switched on, a reset management circuit (116a) executes a reset phase, a configuration phase, and a software runtime phase, where the processing system (10a) starts one or more microprocessors (1020) at respective start-addresses.
Specifically, during the configuration phase, a hardware configuration circuit (108) reads a boot record (BR) from a non-volatile memory (104, 104a) and stores the boot record (BR) to registers (1086). Moreover, the hardware configuration circuit (108) sequentially reads data records of configuration data (CD) from the non-volatile memory (104, 104a) and generates for each data record a respective write request in order to store the data (DATA) of the respective data record to a configuration data client circuit (112) having associated address data indicated in the respective data record. Specifically, the processing system (10a) is configured to process the boot record (BR) stored to the registers (1086) and boot configuration data (BCD2') provided by the configuration data client circuits (112) in order to selectively start (2012) a predetermined microprocessor (1020) at a default start-address, start (2014) the predetermined microprocessor (1020) at a start-address indicated by the boot configuration data (BCD2'), or start (2016) one or more microprocessors (1020) at respective start-addresses as indicated by the boot record.

公开(公告)号：EP4137954A1

公开(公告)日：2023-02-22

申请号：EP22188131.1

申请日：2022-08-01

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

Inventor： DVORAK, Vaclav ,  RENNIG, Fred

IPC: G06F13/42 ,  G06F12/0806 ,  G06F13/40 ,  H04L12/40 ,  G06F13/28 ,  G06F13/38

Abstract: A processing system (10a) is described. The processing system comprises a Serial Peripheral Interface, SPI, communication interface (50), a microprocessor (1020), a memory controller (100) connected to a memory (104, 104b), and two DMA channels (DMA 1 , DMA 2 ) configured to transfer packets between the SPI interface (50) and the memory (104b). In particular, the processing system comprises an edge detector (600, 620) configured to assert a first control signal (IRQ 60 ) in response to a falling edge in the reception signal (RXD), a first hardware timer circuit (60) configure to, when enabled, generate a clock signal (PWM) for the SPI communication interface (50) and a second hardware timer circuit (62) configure to, when enabled, increase a count value and assert a second control signal (IRQ 62 ) in response to determining that the count value reaches a given threshold value.
Specifically, the processing system (10a) is configured to manage a CAN FD Light data transmission mode and/or CAN FD Light data reception mode by using the SPI communication interface. For example, in the CAN FD Light data reception mode, the microprocessor (1020) activates a slave mode of the SPI communication interface (50), enables the first hardware timer circuit (60) and the second hardware timer circuit (62) in response to the first control signal (IRQ 60 ), whereby the second DMA channel (DMA 2 ) transfers packets from the SPI communication interface (50) to the memory (104b), thereby sequentially transferring a reception CAN FD Light frame from the SPI communication interface (50) to the memory (104b), and reads the reception CAN FD Light frame from the memory (104b) in response to the second control signal (IRQ 62 ).

公开(公告)号：EP4086763A1

公开(公告)日：2022-11-09

申请号：EP22168881.5

申请日：2022-04-19

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V.

Inventor： VITTORELLI, Boris ,  BATRA, Simrata ,  SOOD, Vivek Kumar ,  BARANWAL, Deepak

IPC: G06F9/455

Abstract: A processing system (10a) is described. The processing system (10a) comprises a communication system (114a) having a given physical address range (PA) and a plurality of processing cores (102a). Each processing core (102a) has associated a first register (SECM) for storing a first virtual machine ID (VMID), which is inserted into requests (REQ) sent by the respective processing core (102a).
A master circuit (M1) has associated a master interface circuit (MIF1), wherein the master interface circuit (MIF1) has associated a second register (SECM) for storing a second virtual machine ID (VMID[0]), which is inserted into requests (REQ) sent by the second circuit (M1).
A slave circuit (SI) has associated a slave interface circuit (SIF2) configured to selectively forward read or write requests (REQ) addressed to a given address sub-range (PA3) from the communication system (114a) to the first circuit (S1). Specifically, the slave interface circuit (SIF2) has associated a third register (SECS) for storing a third virtual machine ID (VMID_FW[0]) associated with the given first address sub-range (PA3) and is configured to receive a request (REQ) addressed to the given address sub-range (PA3), extract from the request (REQ) a virtual machine ID, determine whether the extracted virtual machine ID corresponds to the third virtual machine ID (VMID_FW[0]), and then either forwards or rejects the request (REQ).

公开(公告)号：EP4064001A1

公开(公告)日：2022-09-28

申请号：EP22162915.7

申请日：2022-03-18

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： COLOMBO, Roberto ,  GROSSIER, Nicolas Bernard

IPC: G06F1/22 ,  G06F1/24

Abstract: A processing system (10a) is described. The processing system comprises a microprocessor, a reset circuit (116a), a non-volatile memory having stored configuration data, a plurality of configuration data clients (112) and a hardware configuration circuit configured to read the configuration data from the non-volatile memory and transmit the configuration data to the configuration data clients (112). In response to switching on the processing system (10a), the processing system (10a) executes a reset phase (DR), a configuration phase (CP1) and a software runtime phase (SW).
In particular, the processing system (10a) comprises a first reset terminal (RPa) having associated a first circuitry (30a, 32a) and a second reset terminal (RPb) having associated a first circuitry (30a, 32a), wherein the first circuitry (30a, 32a) and the second circuitry (30b, 32b) have associated at least one configuration data client (112a, 112b), and wherein the configuration data comprise first mode configuration data (MCDa) for the first terminal (RPa) and second mode configuration data (MCDb) for the second terminal (RPb).
During the reset phase (DR) and the configuration phase (CP1) the first circuitry (30a, 32a) activates a strong pull-down resistance, and the second circuitry (30b, 32b) activate a weak pull-down resistance. Conversely, once the configuration phase is completed, and in particular during the software runtime phase (SW), the first circuitry (30a, 32a) may activate a weak pull-down resistance, e.g., for implementing a bi-direction reset terminal, or a weak pull-up resistance, e.g., for implementing a reset output terminal. Conversely, the second circuitry (30b, 32b) may activate a weak or strong pull-up resistance, e.g., for implementing a reset output terminal, or maintain activated the weak pull-down resistance, e.g., for implementing a reset input terminal.

公开(公告)号：EP4057574A1

公开(公告)日：2022-09-14

申请号：EP22157917.0

申请日：2022-02-22

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

Inventor： RENNIG, Fred ,  DVORAK, Vaclav

IPC: H04L12/40 ,  H03K7/08

Abstract: A circuit (106) comprises a first (24a) and a second (24b) memory, a processing unit (21) and a timer (22). The processing unit generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. Each PWM period has a dominant portion and a recessive portion, and a total duration. The processing unit stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory, wherein the first and second parameter define a shape of the PWM periods. The timer comprises a first register (220) which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter (221) which increases a count number and resets the count number as a function of the value of the first register. A value of the first parameter of a subsequent PWM period is stored into the first register as a function of the value of the first register. The timer comprises a second register (222) which reads from the second memory a value of the second parameter of the current PWM period, and compares the count number of the counter circuit to such value. The second register drives an output pin (230) to a dominant (resp., recessive) value as a function of said comparing the count number of the counter circuit to the value of the second register. A value of the second parameter of a subsequent PWM period is stored into the second register in response to the count number reaching the value stored in the first or second register.

公开(公告)号：EP4027165A1

公开(公告)日：2022-07-13

申请号：EP22305004.8

申请日：2022-01-04

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS ,  STMicroelectronics Application GmbH

Inventor： LETOR, Romeo ,  TIZIANI, Roberto ,  RUSSO, Alfio ,  PAVLIN, Antoine ,  LECCI, Nadia ,  GAERTNER, Manuel

IPC: G01S7/484 ,  H01L23/00

Abstract: An electronic module (10) for generating light pulses, comprising: an electronic card or interposer (2); a LASER-diode (5) lighting module (4); and a LASER-diode driver module (6). The interposer has an edge recess in which the lighting module is completely inserted. The driver module is arranged on top of the interposer and the lighting module. The electrical connections for driving the LASER diodes are obtained without resorting to wire bonding in order to reduce the parasitic inductances.

公开(公告)号：EP4012984A1

公开(公告)日：2022-06-15

申请号：EP21212062.0

申请日：2021-12-02

Applicant: STMicroelectronics Application GmbH

Inventor： RENNIG, Fred ,  NANDLINGER, Rolf

IPC: H04L12/40

Abstract: A processing system is described. The processing system comprises a first CAN XL communication system (50 1 ) and a second CAN XL communication system (50 2 ), wherein each CAN XL communication system (50 1 , 50 2 ) comprises a CAN XL protocol controller configured to generate a NRZ encoded transmission signal (TXD) and receive a NRZ encoded reception signal (RXD). Each CAN XL communication system (50 1 , 50 2 ) is configured to generate a first transmission signal (TXD1) by selecting the NRZ encoded transmission signal (TXD) or a PWM signal generated as a function of the NRZ encoded transmission signal (TXD).
Specifically, the processing system (10a) comprises a bus (22) having a transmission node (TX2) and a reception node (RX2), wherein the bus (22) is configured to receive from each CAN XL communication system (50 1 , 50 2 ) a respective second transmission signal (TXD2) and drive the logic level at the transmission node (TX2) as a function of the logic levels of the second transmission signals (TXD2), and provide to each CAN XL communication system (50 1 , 50 2 ) a respective second reception signal (RXD2) having a logic level determined as a function of the logic level at the reception node (RX2). Moreover, the processing system comprises a switching circuit (24, 224, 306, 308, 52, 520) configured to support a plurality of modes, wherein, in a first mode, the switching circuit (24, 224, 306, 308, 52, 520) is configured to provide the NRZ encoded transmission signals (TXD) of the CAN XL communication systems (50 1 , 50 2 ) as the second transmission signals (TXD2) to the bus system (22), and provide the respective second reception signal (RXD2) received from the bus (22) to the CAN XL protocol controllers (300) of the CAN XL communication system (50 1 , 50 2 ).