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    A METHOD TO MAKE A WEIGHT COMPENSATING/TUNING LAYER ON A SUBSTRATE
    191.
    发明申请
    A METHOD TO MAKE A WEIGHT COMPENSATING/TUNING LAYER ON A SUBSTRATE 审中-公开
    在基板上进行重量补偿/调谐层的方法

    公开(公告)号：WO2005034344A1

    公开(公告)日：2005-04-14

    申请号：PCT/US2004/032062

    申请日：2004-09-29

    Applicant: INTEL CORPORATION

    Inventor： DOROS, Theodore ,  SESHAN, Krishna ,  IYER, Subramani

    IPC: H03H3/04

    CPC classification number: B81B3/0072 ,  B81C2201/0109

    Abstract: Embodiments of the present invention form a weight­compensating/ tuning layer on a structure ( e.g., a silicon wafer with one or more layers of material ( e.g., films)) having variations in its surface topology. The variations in surface topology take the form of thick and thin regions of materials. The weight-compensating/ tuning layer includes narrow and wide regions corresponding to the thick and thin regions, respectively.

    Abstract translation: 本发明的实施例在其表面拓扑结构具有变化的结构（例如，具有一层或多层材料（例如膜）的硅晶片）上形成重量补偿/调谐层。 表面拓扑的变化采取厚薄的材料区域的形式。 重量补偿/调谐层分别包括对应于厚和薄区域的窄且宽的区域。

    METHOD OF FORMING SEMICONDUCTOR DEVICES THROUGH EPITAXY
    193.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICES THROUGH EPITAXY 审中-公开
    通过外延形成半导体器件的方法

    公开(公告)号：WO2004060792A3

    公开(公告)日：2004-10-21

    申请号：PCT/US0333630

    申请日：2003-10-23

    Applicant: FREESCALE SEMICONDUCTOR INC

    Inventor： GOGOI BISHNU

    IPC: B81B3/00 ,  B81C1/00 ,  H01L21/00 ,  H01L21/20 ,  H01L21/36

    CPC classification number: B81B3/001 ,  B81C2201/0109 ,  B81C2201/0177

    Abstract: A method for creating a semiconductor structure is provided. In accordance with the method, a semiconductor substrate (101) is provided over which is disposed a sacrificial layer (103), and which has a thin single crystal semiconductor layer (105) disposed over the sacrificial layer (103). An opening (107) is then created which extends through the semiconductor layer (105) and into the sacrificial layer (103). The semiconductor layer (105) is then epitaxially grown to a suitable device thickness, thereby resulting in a device layer. The semiconductor layer is grown such that the resulting device layer extends over the opening (107), and such that the surface of the portion of the device layer extending over the opening is single crystal silicon.

    Abstract translation: 提供了一种用于创建半导体结构的方法。 根据该方法，提供半导体衬底（101），其上设置有牺牲层（103），并且具有设置在牺牲层（103）上的薄的单晶半导体层（105）。 然后形成延伸穿过半导体层（105）并进入牺牲层（103）的开口（107）。 然后将半导体层（105）外延生长至合适的器件厚度，由此得到器件层。 生长半导体层使得所得器件层在开口（107）上延伸，并且使得在开口上方延伸的器件层的部分的表面是单晶硅。

    DEVICES HAVING VERTICALLY-DISPOSED NANOFABRIC ARTICLES AND METHODS OF MAKING THE SAME
    194.
    发明申请
    DEVICES HAVING VERTICALLY-DISPOSED NANOFABRIC ARTICLES AND METHODS OF MAKING THE SAME 审中-公开
    具有垂直处理的纳米制品的装置及其制造方法

    公开(公告)号：WO2004072335A2

    公开(公告)日：2004-08-26

    申请号：PCT/US2004004107

    申请日：2004-02-12

    Applicant: NANTERO INC ,  JAIPRAKASH VENKATACHALAM C ,  WARD JONATHAN W ,  RUECKES THOMAS ,  SEGAL BRENT M

    Inventor： JAIPRAKASH VENKATACHALAM C ,  WARD JONATHAN W ,  RUECKES THOMAS ,  SEGAL BRENT M

    IPC: B81B3/00 ,  G11C13/02 ,  G11C23/00 ,  H01H59/00 ,  D01F

    CPC classification number: G11C23/00 ,  B81B2201/016 ,  B81B2203/0127 ,  B81C1/00142 ,  B81C2201/0109 ,  B82Y10/00 ,  G11C13/025 ,  G11C14/00 ,  G11C2213/16 ,  G11C2213/77 ,  G11C2213/81 ,  H01H1/0094

    Abstract: Electro-mechanical switches and memory cells using vertically-disposed nanofabric articles and methods of making the same are described. An electro-mechanical device, includes a structure having a major horizontal surface and a channel formed therein. A conductive trace is in the channel; and a nanotube article vertically suspended in the channel, in spaced relation to a vertical wall of the channel. The article is electro-mechanically deflectable in a horizontal direction toward the conductive trace. Under certain embodiments, the vertically suspended extent of the nanotube article is defined by a thin film process. Under certain embodiments, the vertically suspended extent of the nanotube article is about 50 nanometers or less. Under certain embodiments, the nanotube article is clamped with a conducting material disposed in porous spaces between some nanotubes of the nanotube article. Under certain embodiments, the nanotube article is formed from a porous nanofabric. Under certain embodiments, the nanotube article is electromechanically deflectable into contact with the conductive trace and the contact is either a volatile state or non-volatile state depending on the device construction. Under certain embodiments, the vertically oriented device is arranged into various forms of three-trace devices. Under certain embodiments, the channel may be used for multiple independent devices, or for devices that share a common electrode.

    Abstract translation: 描述了使用垂直布置的纳米制品的机电开关和存储单元及其制造方法。 机电装置包括具有主要水平表面和形成在其中的通道的结构。 通道中有导电迹线; 以及垂直悬挂在所述通道中的与所述通道的垂直壁成间隔开的纳米管制品。 该物品在水平方向上可电导向导电迹线偏转。 在某些实施方案中，纳米管制品的垂直悬浮程度由薄膜工艺限定。 在某些实施方案中，纳米管制品的垂直悬浮程度为约50纳米或更小。 在某些实施例中，纳米管制品被夹持在布置在纳米管制品的一些纳米管之间的多孔空间中的导电材料上。 在某些实施方案中，纳米管制品由多孔纳米纤维形成。 在某些实施例中，取决于器件结构，纳米管制品在机电上可偏转成与导电迹线接触，并且触点是易失性状态或非易失性状态。 在某些实施例中，垂直取向的装置被布置成各种形式的三轨迹装置。 在某些实施例中，信道可以用于多个独立设备，或用于共享公共电极的设备。

    METHOD FOR PRODUCING A MICROMECHANICAL DEVICE AND A MICROMECHANICAL DEVICE
    195.
    发明申请
    METHOD FOR PRODUCING A MICROMECHANICAL DEVICE AND A MICROMECHANICAL DEVICE 审中-公开
    制造微机电装置和设备的方法

    公开(公告)号：WO2004071941A2

    公开(公告)日：2004-08-26

    申请号：PCT/DE0303194

    申请日：2003-09-25

    Applicant: BOSCH GMBH ROBERT ,  METZGER LARS ,  FISCHER FRANK

    Inventor： METZGER LARS ,  FISCHER FRANK

    IPC: B81B3/00

    CPC classification number: B81C1/00047 ,  B81B2203/0127 ,  B81C1/0069 ,  B81C2201/0109

    Abstract: The invention relates to a method for producing a micromechanical device and to corresponding micromechanical device consisting of a substrate material (10), a membrane (20) and a hollow space (30) formed in the region of membrane (21) between said substrate and membrane. According to said invention holes (40) are embodied first and foremost in the membrane (20) during a first etching stage and afterwards, the hollow space is produced during a second etching stage.

    Abstract translation: 所以建议制造微机械装置和微型机械装置的方法，所述装置包括一个基底材料（10），膜（20）和其间单细胞结束的在一个膜部分（21）的阀腔（30），并且其中在第一蚀刻工序中，首先 在膜（20）中产生孔（40），并且其中随后通过第二蚀刻步骤产生腔（30）。

    A METHOD FOR FABRICATING A STRUCTURE FOR A MICROELECTROMECHANICAL SYSTEMS (MEMS) DEVICE
    198.
    发明申请
    A METHOD FOR FABRICATING A STRUCTURE FOR A MICROELECTROMECHANICAL SYSTEMS (MEMS) DEVICE 审中-公开
    一种用于制造微电子系统（MEMS）器件的结构的方法

    公开(公告)号：WO2003069413A1

    公开(公告)日：2003-08-21

    申请号：PCT/US2002/013442

    申请日：2002-04-29

    Applicant: IRIDIGM DISPLAY CORPORATION ,  MILES, Mark, W.

    Inventor： MILES, Mark, W.

    IPC: G03F7/20

    CPC classification number: G02B26/001 ,  B81B2201/042 ,  B81B2203/0315 ,  B81C1/00396 ,  B81C2201/0109 ,  B81C2203/0136

    Abstract: The invention provides a microfabrication process which may be used to manufacture a MEMS device. The process comprises depositing one or a stack of layers on a base layer, said one layer or an uppermost layer in said stack of layers being a sacrificial layer; patterning said one or a stack of layers to provide at least one aperture therethrough through which said base layer is exposed; depositing a photosensitive layer over said one or a stack of layers; and passing light through said at least one aperture to expose said photosensitive layer.

    Abstract translation: 本发明提供了可用于制造MEMS装置的微细加工方法。 该方法包括在基底层上沉积一层或一叠层，所述层中的所述一层或最上层为牺牲层; 图案化所述一层或一叠层以提供穿过其中的所述基层暴露的至少一个孔; 在所述一层或一叠层上沉积感光层; 并使光通过所述至少一个孔以暴露所述感光层。

    ＭＥＭＳ素子の製造方法
    199.
    发明申请
    ＭＥＭＳ素子の製造方法 审中-公开
    MEMS元件制造方法

    公开(公告)号：WO2003055789A1

    公开(公告)日：2003-07-10

    申请号：PCT/JP2002/013128

    申请日：2002-12-16

    Applicant: ソニー株式会社 ,  池田 浩一 ,  木下 隆

    Inventor： 池田 浩一 ,  木下 隆

    IPC: B81B3/00

    CPC classification number: B81C1/00611 ,  B81B2201/042 ,  B81B2203/0118 ,  B81C2201/0109 ,  B81C2201/0119 ,  B81C2201/0125

    Abstract: A method for manufacturing an MEMS element for flattening a drive side electrode surface, reducing irregularities of beam shape, improving performance, and improving performance uniformity. The method includes a step of forming a substrate side electrode on a substrate, a step of forming a fluid film before or after formation of a sacrificial layer, a step of forming a beam having a drive side electrode on a flattened surface, and a step of removing the sacrificial layer.

    Abstract translation: 一种用于制造用于使驱动侧电极表面平坦化的MEMS元件的方法，减少光束形状的不规则性，提高性能并提高性能均匀性。 该方法包括在基板上形成基板侧电极的步骤，在形成牺牲层之前或之后形成流体膜的步骤，在平坦表面上形成具有驱动侧电极的光束的步骤，以及步骤 去除牺牲层。

    MICROELECTRONIC MECHANICAL SYSTEM AND METHODS
    200.
    发明申请
    MICROELECTRONIC MECHANICAL SYSTEM AND METHODS 审中-公开
    微电子机械系统与方法

    公开(公告)号：WO2003023849A1

    公开(公告)日：2003-03-20

    申请号：PCT/US2002/027822

    申请日：2002-08-29

    Applicant: SILICON LIGHT MACHINES

    Inventor： BRUNER, Mike

    IPC: H01L23/02

    CPC classification number: B81C1/00484 ,  B81B2201/0271 ,  B81B2203/0136 ,  B81C1/00246 ,  B81C1/00333 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0136 ,  B81C2203/0735

    Abstract: The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer (211) that preferably comprises silicon oxide and/or silicon nitride and which is formed over an etch resistant substrate (203). A patterned device layer (206), preferably comprising silicon nitride, is embedded in a sacrificial material (205, 209), preferably comprising polysilicon, and is disposed between the etch resistant substrate (203) and the capping layer (211). Access trenches or holes (219) are formed into the capping layer (211) and the sacrificial material (205, 209) is selectively etched through the access trenches (219) such that portions of the device layer (206) are released from the sacrificial material (205, 209). The etchant preferably comprises a noble gas fluoride N g F 2x (wherein Ng = Xe, Kr or Ar: and where x = 1, 2 or 3). After etching that sacrificial material (205, 209), the access trenches (219) are sealed to encapsulate (241) released portions the device layer (206) between the etch resistant substrate (203) and the capping layer (211). The current invention is particularly useful for fabricating MEMs devices, multiple cavity devices and devices with multiple release features.

    Abstract translation: 本发明提供了包封的释放结构，其中间体及其制备方法。 多层结构具有优选包括氧化硅和/或氮化硅并且形成在耐蚀刻衬底（203）上的覆盖层（211）。 优选地包括氮化硅的图案化器件层（206）嵌入在牺牲材料（205,209）中，优选地包括多晶硅，并且设置在耐蚀刻衬底（203）和覆盖层（211）之间。 进入沟槽或孔（219）形成为覆盖层（211），并且牺牲材料（205,209）通过通路沟槽（219）被选择性蚀刻，使得器件层（206）的部分从牺牲层 材料（205,209）。 蚀刻剂优选包含惰性气体氟化物NgF2x（其中Ng = Xe，Kr或Ar：其中x = 1,2或3）。 在蚀刻该牺牲材料（205,209）之后，密封接入沟槽（219）以将该器件层（206）的封装（241）释放部分封装在耐蚀刻衬底（203）和覆盖层（211）之间。 本发明对于制造具有多个释放特征的MEM器件，多腔器件和器件特别有用。

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