Abstract:
The invention concerns a system comprising a central unit (CPU) associated with one or several input-output control units (Ctl1-Ctl4) and a redundancy disk sub-system (MD), divided into logical units and under the control of two redundant disk controllers (SP-A, SP-B). These are attached to the input-output controller(s) by buses likewise redundant. One first part of the logical units is assigned to the first disk controller (SP-A) and the other part to the second disk controller (SP-B). When a logical unit, assigned to the first disk controller (SP-A) is accessed, the state of the second disk controller (SP-B) is monitored by the backup path. If a breakdown of the second disk controller (SP-B) is detected, all the logical units are toggled on to the first (SP-A) and are assigned thereto. A crippled mode is initiated and access to resources is carried out by the backup path. The invention is applicable to data processing.
Abstract:
A computer network comprises a number of storage controllers (3-1 to 3-M), each coupled to one of a plurality of storage arrays (4-1 to 4-M), each storage array including at least one mass storage device (MSD). Each storage controller may be coupled to at least one host processing system (2-1 to 2-M) and to at least one other storage controller to control access of the host processing systems to the mass storage devices. Multiple copies of data are maintained in storage arrays that are geographically remote to each other, such that any copy can be accessed by any host. Each storage controller includes an interface (14) with a host that emulates a mass storage device independent of the storage device type and an interface (15) with a local storage array that emulates a host independent of the host type. Hosts access stored data using virtual addressing. The storage controllers provide automatic back-up and error correction as well as write protection of back-up copies.
Abstract:
The invention provides for a data storage apparatus including a first bus (104), a second bus (106), and a storage module (102) having a first and second output with the first output being connected to the first bus (104) and a second output being connected to the second bus (106). A first buffer storage (108) is connected to the first bus (104), and a second buffer storage (110) is connected to the second bus (106). The second buffer storage (110) includes an error correction module (110c), and first and second network adapters (112, 114) are connected to the first (104) and second (106) buses, respectively. The first network adapter (112) also includes a connection to the first buffer (108). A processor (120) in the apparatus includes a first processor means for transferring the data using a first path through the first output in the storage module (102) to the first buffer storage (108) and from the first buffer storage (108) to the first network adapter (112). A second processor means (120) is provided for transferring data using a second path through the second output to the second buffer storage (110) through the error correction module (110c) and from the second buffer storage (110) to the second network adapter (114), wherein the second processor means is responsive to an error in the storage module (102).
Abstract:
A mass memory system for digital computers is disclosed. The system has a plurality of disk drives (250-255) coupled to a plurality of small buffers (240-245). An Error Correction Controller (260 and 270) is coupled to a plurality of X-bar switches (210-215), the X-bar switches being connected between each disk drive and its buffers. Data is read from and written to the disk drives in parallel and error correction is also performed in parallel. The X-bar switches are used to couple and decouple functional and nonfunctional disk drives to the system as necessary. Likewise, the buffers can be disconnected from the system should they fail. The parallel architecture, combined with a Reed-Solomon error detection and correction scheme and X-bar switches allows the system to tolerate and correct any two failed drives, allowing for high fault-tolerance operation.
Abstract:
The present invention discloses a disk array, which is applied to a storage system including the dual controller disk array and a server. The disk array includes a disk frame and two controller nodes. Each controller node includes a switch, where a port of the switch is connected to a port of a switch of a peer controller node. Each controller node is configured to detect whether the peer controller node is invalid through the port. When it has been detected that the peer controller node is invalid, a local controller node enables the peer controller node to send, through the port of the switch of the peer controller node, received data sent by the server to a port of a switch of the local controller node.
Abstract:
The present invention relates to a storage device in which the MR-IOV is applied to an internal network of a storage controller. Data path failover can be executed in the storage device. The internal network of the storage controller is configured to enable the access of a virtual function (VF) "VF 0:0, 1" of each endpoint device (EDO-ED2) from a root port RP0. Likewise, "VF 1:0, 1" of each endpoint device can be accessed from a root port RP1. In a first data path from the RP0 to ED0 in a normal state, "VF 0:0, 1" and "MVF 0, 0" are connected by VF mapping. When a failure occurs on the first data path, the MR-PCIM executes the VF migration, whereby in the second data path from the RP1 to ED0, "VF 1:0, 1" and "MVF 0, 0" are connected by VF mapping. As a result, failover to the second data path is realized.
Abstract:
In a storage device expandable through serially coupling two or more additional enclosures (20), each including a first additional controller (21) and a second additional controller (22), to a controller enclosure (10), including a first controller (11) and a second controller (12), a first route is formed by serially coupling the first controller (11) of the controller enclosure (10) to the first additional controllers (21) of the additional enclosures (20) in the order of adding the additional enclosures (20) and a second route is formed by serially coupling the second controller (12) of the controller enclosure (10) to the second additional controllers (22) of the additional enclosures (20) in an order different from that of adding the additional enclosures (20).