公开(公告)号：WO98049619A1

公开(公告)日：1998-11-05

申请号：PCT/FR1998/000814

申请日：1998-04-23

IPC: G06F11/20 ,  G06F11/22

CPC classification number: G06F11/2092 ,  G06F11/2007 ,  G06F11/201 ,  G06F11/2089 ,  G06F11/22

Abstract: The invention concerns a system comprising a central unit (CPU) associated with one or several input-output control units (Ctl1-Ctl4) and a redundancy disk sub-system (MD), divided into logical units and under the control of two redundant disk controllers (SP-A, SP-B). These are attached to the input-output controller(s) by buses likewise redundant. One first part of the logical units is assigned to the first disk controller (SP-A) and the other part to the second disk controller (SP-B). When a logical unit, assigned to the first disk controller (SP-A) is accessed, the state of the second disk controller (SP-B) is monitored by the backup path. If a breakdown of the second disk controller (SP-B) is detected, all the logical units are toggled on to the first (SP-A) and are assigned thereto. A crippled mode is initiated and access to resources is carried out by the backup path. The invention is applicable to data processing.

Abstract translation: 本发明涉及一种系统，包括与一个或多个输入输出控制单元（Ct1-Ct14）和冗余磁盘子系统（MD）相关联的中央单元（CPU），其被划分为逻辑单元并且在两个冗余磁盘 控制器（SP-A，SP-B）。 这些通过同样冗余的总线连接到输入 - 输出控制器。 逻辑单元的第一部分被分配给第一磁盘控制器（SP-A），另一部分分配给第二磁盘控制器（SP-B）。 当分配给第一个磁盘控制器（SP-A）的逻辑单元被访问时，备份路径监视第二个磁盘控制器（SP-B）的状态。 如果检测到第二盘控制器（SP-B）的故障，则将所有逻辑单元切换到第一（SP-A）并被分配给其。 发起瘫痪模式，并通过备份路径执行对资源的访问。 本发明适用于数据处理。

公开(公告)号：WO98044423A1

公开(公告)日：1998-10-08

申请号：PCT/US1998/004924

申请日：1998-03-11

IPC: G06F3/06 ,  G06F11/14 ,  G06F11/20 ,  G06F13/16 ,  G06F12/16 ,  G06F13/14

CPC classification number: G06F13/1657 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0689 ,  G06F11/201 ,  G06F11/2058 ,  G06F11/2069 ,  G06F11/2071 ,  G06F11/2094 ,  G06F11/2097 ,  Y10S707/99953 ,  Y10S707/99954 ,  Y10S707/99955

Abstract: A computer network comprises a number of storage controllers (3-1 to 3-M), each coupled to one of a plurality of storage arrays (4-1 to 4-M), each storage array including at least one mass storage device (MSD). Each storage controller may be coupled to at least one host processing system (2-1 to 2-M) and to at least one other storage controller to control access of the host processing systems to the mass storage devices. Multiple copies of data are maintained in storage arrays that are geographically remote to each other, such that any copy can be accessed by any host. Each storage controller includes an interface (14) with a host that emulates a mass storage device independent of the storage device type and an interface (15) with a local storage array that emulates a host independent of the host type. Hosts access stored data using virtual addressing. The storage controllers provide automatic back-up and error correction as well as write protection of back-up copies.

Abstract translation: 计算机网络包括多个存储控制器（3-1至3-M），每个存储控制器分别耦合到多个存储阵列（4-1至4-M）中的一个，每个存储阵列包括至少一个大容量存储设备 MSD）。 每个存储控制器可以耦合到至少一个主机处理系统（2-1至2-M）和至少一个其他存储控制器，以控制主处理系统对大容量存储设备的访问。 多个数据副本被保存在地理上彼此远的存储阵列中，以便任何主机可以访问任何副本。 每个存储控制器包括具有与独立于存储设备类型模拟大容量存储设备的主机的接口（14）和具有独立于主机类型的模拟主机的本地存储阵列的接口（15）。 主机使用虚拟寻址访问存储的数据。 存储控制器提供自动备份和纠错以及备份副本的写保护。

公开(公告)号：WO1997007455A2

公开(公告)日：1997-02-27

申请号：PCT/GB1996001837

申请日：1996-07-30

Applicant: SYMBIOS LOGIC INC. ,  GILL, David, Alan

Inventor： SYMBIOS LOGIC INC. ,  GILL, David, Alan ,  DULAC, Keith, Bernard ,  PHILLIPS, Grover, George

IPC: G06F11/00

CPC classification number: G06F11/201 ,  G06F11/1076 ,  G06F2201/85 ,  G06F2211/1014 ,  H04N7/17336

Abstract: The invention provides for a data storage apparatus including a first bus (104), a second bus (106), and a storage module (102) having a first and second output with the first output being connected to the first bus (104) and a second output being connected to the second bus (106). A first buffer storage (108) is connected to the first bus (104), and a second buffer storage (110) is connected to the second bus (106). The second buffer storage (110) includes an error correction module (110c), and first and second network adapters (112, 114) are connected to the first (104) and second (106) buses, respectively. The first network adapter (112) also includes a connection to the first buffer (108). A processor (120) in the apparatus includes a first processor means for transferring the data using a first path through the first output in the storage module (102) to the first buffer storage (108) and from the first buffer storage (108) to the first network adapter (112). A second processor means (120) is provided for transferring data using a second path through the second output to the second buffer storage (110) through the error correction module (110c) and from the second buffer storage (110) to the second network adapter (114), wherein the second processor means is responsive to an error in the storage module (102).

Abstract translation: 本发明提供了一种包括第一总线（104），第二总线（106）和存储模块（102）的数据存储装置，该存储模块具有第一和第二输出，第一输出端连接到第一总线（104），第 第二输出端连接到第二总线（106）。 第一缓冲存储器（108）连接到第一总线（104），第二缓冲存储器（110）连接到第二总线（106）。 第二缓冲存储器（110）包括错误校正模块（110c），并且第一和第二网络适配器（112,114）分别连接到第一（104）和第二（106）总线。 第一网络适配器（112）还包括到第一缓冲器（108）的连接。 装置中的处理器（120）包括第一处理器装置，用于使用通过存储模块（102）中的第一输出的第一路径将数据传送到第一缓冲存储器（108），并且从第一缓冲存储器（108）到 第一网络适配器（112）。 提供第二处理器装置（120），用于使用通过第二输出的第二路径通过错误校正模块（110c）将数据传送到第二缓冲存储器（110），并且从第二缓冲存储器（110）传送到第二网络适配器 （114），其中所述第二处理器装置响应于所述存储模块（102）中的错误。

公开(公告)号：WO1991015822A1

公开(公告)日：1991-10-17

申请号：PCT/US1991002315

申请日：1991-04-03

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  HENSON, Larry, P. ,  GAJJAR, Kumar ,  POWERS, David, T. ,  IDLEMAN, Thomas, E.

IPC: G06F11/20

CPC classification number: G06F11/10 ,  G06F11/0757 ,  G06F11/1076 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/201 ,  G06F11/2089 ,  G06F11/2094 ,  G06F2211/1057 ,  G11B20/1833

Abstract: A mass memory system for digital computers is disclosed. The system has a plurality of disk drives (250-255) coupled to a plurality of small buffers (240-245). An Error Correction Controller (260 and 270) is coupled to a plurality of X-bar switches (210-215), the X-bar switches being connected between each disk drive and its buffers. Data is read from and written to the disk drives in parallel and error correction is also performed in parallel. The X-bar switches are used to couple and decouple functional and nonfunctional disk drives to the system as necessary. Likewise, the buffers can be disconnected from the system should they fail. The parallel architecture, combined with a Reed-Solomon error detection and correction scheme and X-bar switches allows the system to tolerate and correct any two failed drives, allowing for high fault-tolerance operation.

公开(公告)号：EP1668512B1

公开(公告)日：2013-09-18

申请号：EP04756088.3

申请日：2004-06-23

Applicant: Sierra Logic

Inventor： STEINMETZ, Joseph H. ,  KOMPELLA, Murthy ,  WAKELEY, Matthew P.

IPC: G06F3/06

CPC classification number: G06F3/0661 ,  G06F3/0607 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0617 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0689 ,  G06F11/201 ,  G06F11/2089 ,  H04L67/1097

公开(公告)号：EP2610750A1

公开(公告)日：2013-07-03

申请号：EP12187557.9

申请日：2012-10-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Li, Xuhui

IPC: G06F11/20 ,  G06F3/06

CPC classification number: G06F3/0635 ,  G06F3/0617 ,  G06F3/0689 ,  G06F11/201 ,  G06F11/2092

Abstract: The present invention discloses a disk array, which is applied to a storage system including the dual controller disk array and a server. The disk array includes a disk frame and two controller nodes. Each controller node includes a switch, where a port of the switch is connected to a port of a switch of a peer controller node. Each controller node is configured to detect whether the peer controller node is invalid through the port. When it has been detected that the peer controller node is invalid, a local controller node enables the peer controller node to send, through the port of the switch of the peer controller node, received data sent by the server to a port of a switch of the local controller node.

Abstract translation: 本发明公开了一种磁盘阵列，其应用于包括双控制盘阵列和服务器的存储系统。 磁盘阵列包括一个磁盘框架和两个控制器节点。 每个控制器节点包括交换机，其中交换机的端口连接到对等控制器节点的交换机的端口。 每个控制器节点配置为通过端口检测对等控制器节点是否无效。 当检测到对端控制器节点无效时，本地控制器节点使对等控制器节点能够通过对等控制器节点的交换机的端口将接收到的服务器发送的数据发送到交换机的交换机的端口 本地控制器节点。

公开(公告)号：EP1840746B1

公开(公告)日：2012-05-02

申请号：EP07251026.6

申请日：2007-03-13

Applicant: Hitachi, Ltd.

Inventor： Komatsu, Yuki, ,  Aoki, Makoto

IPC: G06F11/20

CPC classification number: G06F11/201 ,  G06F3/0611 ,  G06F3/0635 ,  G06F3/067

公开(公告)号：EP2369485A1

公开(公告)日：2011-09-28

申请号：EP11161660.3

申请日：2009-04-20

Applicant: Hitachi Ltd.

Inventor： Tanaka Katsuya ,  Shimada Kentaro

IPC: G06F11/20

CPC classification number: G06F11/201

Abstract: The present invention relates to a storage device in which the MR-IOV is applied to an internal network of a storage controller. Data path failover can be executed in the storage device. The internal network of the storage controller is configured to enable the access of a virtual function (VF) "VF 0:0, 1" of each endpoint device (EDO-ED2) from a root port RP0. Likewise, "VF 1:0, 1" of each endpoint device can be accessed from a root port RP1. In a first data path from the RP0 to ED0 in a normal state, "VF 0:0, 1" and "MVF 0, 0" are connected by VF mapping. When a failure occurs on the first data path, the MR-PCIM executes the VF migration, whereby in the second data path from the RP1 to ED0, "VF 1:0, 1" and "MVF 0, 0" are connected by VF mapping. As a result, failover to the second data path is realized.

Abstract translation: 本发明涉及其中所述MR-IOV是施加到一个存储控制器的内部网络的存储装置。 数据路径故障切换可以在存储装置中执行。 所述存储控制器的内部网络被配置为使得一个虚拟功能（VF）“VF 0：0,1”的访问从根端口RP0每个端点设备（EDO-ED2）的。 同样地，“VF 1：0,1”每个端点设备可以从根端口RP1进行访问。 在从RP0到ED0在正常状态下的第一数据路径，“VF 0：0,1”和“MVF 0,0”通过VF映射连接。 当第一数据路径上发生了故障的，则MR-PCIM执行VF迁移，由此在从RP1到ED0，“VF 1：0,1”第二数据路径和“MVF 0,0”通过VF连接 映射。 其结果是，故障转移到第二数据路径实现。

公开(公告)号：EP2360572A1

公开(公告)日：2011-08-24

申请号：EP11151061.6

申请日：2011-01-17

Applicant: Fujitsu Limited

Inventor： Kanayama, Tomoyuki ,  Maeda Shigeyuki ,  Tsukamoto Nina

IPC: G06F3/06 ,  G06F11/20

CPC classification number: G06F3/0635 ,  G06F3/0617 ,  G06F3/067 ,  G06F11/201 ,  G06F11/2089

Abstract: In a storage device expandable through serially coupling two or more additional enclosures (20), each including a first additional controller (21) and a second additional controller (22), to a controller enclosure (10), including a first controller (11) and a second controller (12), a first route is formed by serially coupling the first controller (11) of the controller enclosure (10) to the first additional controllers (21) of the additional enclosures (20) in the order of adding the additional enclosures (20) and a second route is formed by serially coupling the second controller (12) of the controller enclosure (10) to the second additional controllers (22) of the additional enclosures (20) in an order different from that of adding the additional enclosures (20).

Abstract translation: 在可扩展的存储设备中，每个包括第一附加控制器（21）和第二附加控制器（22）的两个或多个额外的外壳（20）通过串联地耦合到包括第一控制器（11）的控制器外壳（10） 和第二控制器（12），通过将所述控制器外壳（10）的所述第一控制器（11）以附加的外壳（20）的所述第一附加控制器（21）顺序地耦合到所述第二控制器（12）的顺序， 通过将控制器外壳（10）的第二控制器（12）与附加外壳（20）的第二附加控制器（22）以不同于添加的外壳（20）的顺序串联地形成另外的外壳（20）和第二路由 附加的外壳（20）。

公开(公告)号：EP2182443B1

公开(公告)日：2011-08-03

申请号：EP09251131.0

申请日：2009-04-20

Applicant: Hitachi Ltd.

Inventor： Tanaka, Katsuya ,  Shimada, Kentaro

IPC: G06F11/20

CPC classification number: G06F11/201