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    STREET DECREASE FOR FLIP CHIP PACKAGE
    201.
    发明专利
    STREET DECREASE FOR FLIP CHIP PACKAGE 失效

    公开(公告)号：JP2000036517A

    公开(公告)日：2000-02-02

    申请号：JP16253399

    申请日：1999-06-09

    Applicant: ST MICROELECTRONICS INC

    Inventor： ANTHONY M CHU

    IPC: H01L21/60 ,  H01L21/56 ,  H01L29/06

    Abstract: PROBLEM TO BE SOLVED: To provide a technique for strengthening a connecting force between a flip chip IC and a substrate. SOLUTION: At least either an IC or a substrate is provided with an anchor (fixed) point 702 so that a connecting force between the IC and the substrate can be improved. The anchor (fixed) point 702 can be a through-hole passing through the IC or the substrate, or a groove, or a surface recessed part such as a notched part. The anchor (fixed) point 702 can be packed with a lower side packing substrate during under-fill, that is, a lower side packing processing period (302) This anchor (fixed) point 702 can apply additional mechanical strength to a bonding force, that is, the connecting force between the IC and the substrate.

    PICTURE MEMORY MAPPING FOR MINIMIZING MEMORY BANDWIDTH IN COMPRESSION AND EXPANSION OF DATA SEQUENCE
    202.
    发明专利
    PICTURE MEMORY MAPPING FOR MINIMIZING MEMORY BANDWIDTH IN COMPRESSION AND EXPANSION OF DATA SEQUENCE 失效

    公开(公告)号：JPH11316708A

    公开(公告)日：1999-11-16

    申请号：JP32854898

    申请日：1998-11-18

    Applicant: ST MICROELECTRONICS INC

    Inventor： BALAKRISHNAN JEYENDRAN ,  OWEN JEFFERSON E

    IPC: G06F12/04 ,  H04N5/907 ,  H04N7/26 ,  H04N7/50 ,  H04N9/804 ,  H04N9/808 ,  H04N7/24

    Abstract: PROBLEM TO BE SOLVED: To store and retrieve mass data which are required at the time of being sequentially accessed by storing each succeeding data of a stripe in a word in a memory having an adjacent word address after a word storing data of the preceding row. SOLUTION: A memory buffer 210 belongs to a memory of a device having a main decoder. A position in the memory is selected as a 1st word 208 and data in a 1st row of a 1st stripe 202 of a picture are stored in the word 208. Succeeding data in the 1st row one stored in the succeeding work 214. This is continuously executed about the entire stripe 202. One row of the stripe 202 is stored in a word just after a word storing a preceding row of the stripe 202. A 1st row of the succeeding stripe 204 is stored in a word 217 which is next to a word 215 storing data of the last row of the preceding stripe 202 and has a word address that is adjacent to it.

    METHOD AND DEVICE FOR FAST SWITCHING BETWEEN FLOATING-POINT INSTRUCTION AND MULTIMEDIA INSTRUCTION USING TWO SETS OF REGISTERS
    203.
    发明专利
    METHOD AND DEVICE FOR FAST SWITCHING BETWEEN FLOATING-POINT INSTRUCTION AND MULTIMEDIA INSTRUCTION USING TWO SETS OF REGISTERS 失效

    公开(公告)号：JPH11288372A

    公开(公告)日：1999-10-19

    申请号：JP37431698

    申请日：1998-12-28

    Applicant: ST MICROELECTRONICS INC

    Inventor： DAVID WON

    IPC: G06F9/30 ,  G06F9/312 ,  G06F9/318 ,  G06F9/34 ,  G06F9/38 ,  G06F9/46

    Abstract: PROBLEM TO BE SOLVED: To provide an improved device which can preserve and recover states of various registers in a microprocessor by providing a means to recover 1st sate information from a 1st register set when a 2nd task is switched to a 1st task if the 1st state information is not corrected. SOLUTION: A means is provided to recover 1st state information from a 1st register set when a 2nd task is switched to a 1st task as long as the 1st state information is not corrected. This device includes two sets of registers, i.e., registers 0 and 1. When a CPU stores a floating-point state or environment in a memory as an image, this state or environment is stored in an additional internal register as a copy. Then necessary information is recovered from the additional register when the CPU must recover the state or environment. Thus, it's possible to evade a case where the image is loaded again from a main memory.

    CAPACITIVE SEMICONDUCTOR USER INPUT DEVICE
    204.
    发明专利
    CAPACITIVE SEMICONDUCTOR USER INPUT DEVICE 失效

    公开(公告)号：JPH11288354A

    公开(公告)日：1999-10-19

    申请号：JP579699

    申请日：1999-01-12

    Applicant: ST MICROELECTRONICS INC

    Inventor： KRAMER ALAN

    IPC: G06F3/041 ,  G06F3/033 ,  G06F3/044 ,  G06F3/048 ,  G06T1/00 ,  G06F3/03

    Abstract: PROBLEM TO BE SOLVED: To provide an inexpensive non-mechanical pointer position controller of a small size by detecting the change of fingerprint pattern of a user and giving input to a computer system, based on the change of the fingerprint pattern. SOLUTION: The change of fingerprint pattern of a user is detected and the input is given to a computer system, based on the change of the fingerprint pattern. A user input device 19 has a detection element 21 which detects the thumb of the user or its motion as shown by an imaginary line 23 to control the X and Y positions of a pointer 17 on a screen 15. The element 21 also detects the change of the peak width of a fingerprint or the lifting of a finger on the element 21. The change caused on the element 21 by the finger pressure is detected to control the Z position of the pointer 17 or the button input given to a processor. A pointer controller 25 receives the output from the device 19 and generates the output to control the position of the pointer 17 on the screen 15.

    PRE-PROGRAMMED MEMORY IN WHICH SPEED AND POWER CONSUMPTION ARE IMPROVED
    205.
    发明专利
    PRE-PROGRAMMED MEMORY IN WHICH SPEED AND POWER CONSUMPTION ARE IMPROVED 失效

    公开(公告)号：JPH11242895A

    公开(公告)日：1999-09-07

    申请号：JP32394698

    申请日：1998-11-13

    Applicant: ST MICROELECTRONICS INC

    Inventor： ARTIERI ALAIN

    IPC: G11C17/18 ,  G11C7/00 ,  G11C17/12

    Abstract: PROBLEM TO BE SOLVED: To save power and also to attain the quick access by reorganize a memory so that the number of 1s of memory cells of respective rows and columns of an array become smaller than that of 0s of the cells to reduce the number of transistors to be connected to bit lines. SOLUTION: When the number of 1s in respective rows and respective columns of data cells of a matrix shaped array is larger than the number of 0s, the reorganizing of the memory is performed by inverting the data cells alternately every row and column and by performing inversions repeatedly until all rows and columns become so as to have at least the number of 1s equal to that of the number of 0s. Then, flag data at that time are stored in corresponding flag memories being in the cells to be connected to inverters 122. Transistors of only, memory cells having 1s are connected to bit lines 116. As a result, the number of running transistors is reduced by reorganizing a memory 100 while reducing the number of cells having is in this manner. Moreover, a data circuit array has cells for storages 110 of the reorganized array, a data read circuit and an address circuit and the inverting of bits are performed by XOR gates 120.

    METHOD AND APPARATUS FOR COMMUNICATING WITH A HOST
    209.
    发明申请
    METHOD AND APPARATUS FOR COMMUNICATING WITH A HOST 审中-公开
    与主机通信的方法和设备

    公开(公告)号：WO0246936A3

    公开(公告)日：2003-02-27

    申请号：PCT/US0146289

    申请日：2001-12-03

    Applicant: SCHLUMBERGER SYSTEMS SA ,  SCHLUMBERGER TECHNOLOGIES OPERATING LTD ,  ST MICROELECTRONICS INC

    Inventor： LEYDIER ROBERT ANTOINE ,  POMET CHRITOPHE ALAIN

    IPC: G06F3/00 ,  G06F13/40 ,  G06K17/00 ,  H03K19/0175 ,  G06F13/42

    CPC classification number: G06F13/4086

    Abstract: A method and apparatus is disclosed. In one embodiment, a smart card has an IC with voltage conditioning circuitry and a pull-up resistor. The card is capable of signaling a host over a bus using the resistor selectively coupled to a voltage output of the conditioning circuitry and a first output of the card. The conditioning circuitry output is selectively coupled to the first output through the resistor, responsive to being powered by the bus but not transmitting. This tends to pull up the first output to the voltage level of the voltage source, making the card capable of being detected by the host upon the bus being driven by a host. Selectively disconnecting the resistor while transmitting or receiving results in a more balanced output. Since the resistor and conditioning circuitry are an integrated part of the IC, no separate contact is required for voltage to the resistor, permiting compatibity with the contact configuration of certain existing smart cards, and eliminating a pull-up resistor or conditioning circuitry in a card reader.

    Abstract translation: 公开了一种方法和装置。 在一个实施例中，智能卡具有带电压调节电路和上拉电阻的IC。 该卡能够使用选择性耦合到调节电路的电压输出端和卡的第一输出端的电阻器通过总线向主机发送信号。 响应于由总线供电但不传输，调节电路输出通过电阻选择性地耦合到第一输出。 这倾向于将第一输出拉到电压源的电压电平，使得该卡能够在总线由主机驱动时被主机检测到。 在发送或接收时选择性地断开电阻，可以获得更均衡的输出。 由于电阻和调节电路是IC的集成部分，因此不需要为电阻器提供电压的单独接触，允许与某些现有智能卡的接触配置兼容，并且消除卡中的上拉电阻或调节电路 读者。

    NOISE SHAPED INTERPOLATOR AND DECIMATOR APPARATUS AND METHOD
    210.
    发明申请
    NOISE SHAPED INTERPOLATOR AND DECIMATOR APPARATUS AND METHOD 审中-公开
    噪声形状的插入器和分离器装置和方法

    公开(公告)号：WO2005015752A8

    公开(公告)日：2005-07-07

    申请号：PCT/US2004025323

    申请日：2004-08-04

    Applicant: ST MICROELECTRONICS INC

    Inventor： NORSWORTHY STEVEN R ,  REDGRAVE JASON RUPERT

    IPC: H03H17/06 ,  H04B20060101 ,  H04L27/10

    CPC classification number: H03H17/0628 ,  G06F5/14 ,  G06F2205/061 ,  H03H17/0614

    Abstract: Improved interpolator (1304) and decimator (1324) apparatus and methods, including the addition of an elastic storage element (192) comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified imterpolator and decimator.

    Abstract translation: 包括添加弹性存储元件（192）的改进的内插器（1304）和抽取器（1324）设备和方法包括有利地允许吸收采样时钟中的短期变化的FIFO，并且还提供用于控制 Δ-Σ调制的基于模N计数器的采样时钟发生器。 与delta-sigma调制器和计数器组合在一起的弹性元件创建了一个噪音形状的频率锁定环，无需额外的元件，从而得到简化的插入器和抽取器。

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