中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

4906 records (took 0.035 seconds)

    CIRCUIT FOR READING A CHARGE RETENTION ELEMENT FOR TEMPORAL MEASUREMENT
    201.
    发明申请
    CIRCUIT FOR READING A CHARGE RETENTION ELEMENT FOR TEMPORAL MEASUREMENT 审中-公开
    读取用于时间测量的充电保持元件的电路

    公开(公告)号：WO2008012462A3

    公开(公告)日：2008-04-03

    申请号：PCT/FR2007051700

    申请日：2007-07-20

    Applicant: ST MICROELECTRONICS SA ,  LA ROSA FRANCESCO

    Inventor： LA ROSA FRANCESCO

    IPC: G11C27/00 ,  G11C7/10

    CPC classification number: G11C7/06 ,  G04F10/10 ,  G11C7/062

    Abstract: The invention relates to a method and a circuit for reading an electronic charge retention element (10) for a temporal measurement, of the type comprising at least one capacitive element (C1, C2) whose dielectric exhibits a leakage and a transistor with insulated control terminal (5) for reading the residual charges, the reading circuit comprising: two parallel branches between two supply terminals, each branch comprising at least one transistor of a first type (P1, P2) and one transistor of a second type (N3, 5), the transistor of the second type of one of the branches consisting of that of the element to be read and the transistor of the second type of the other branch receiving, on its control terminal, a staircase signal (VDAC), the respective drains of the transistors of the first type being connected to the respective inputs of a comparator (135) whose output (OUT) provides an indication of the residual voltage in the charge retention element.

    Abstract translation: 本发明涉及一种用于读取用于时间测量的电子电荷保持元件（10）的方法和电路，其类型包括其电介质呈现泄漏的至少一个电容元件（C1，C2）和具有绝缘控制端子的晶体管 （5）用于读取剩余电荷，所述读取电路包括：两个电源端之间的两个并联支路，每个支路包括至少一个第一类型的晶体管（P1，P2）和一个第二类型晶体管（N3,5） ，第二类型的一个分支的晶体管由待读取的元件的晶体管和第二类型的另一支路的晶体管在其控制端子上接收一个阶梯信号（VDAC），相应的漏极 第一类型的晶体管连接到比较器（135）的相应输入，其比较器（135）的输出（OUT）提供电荷保留元件中的残余电压的指示。

    CHARGE RETENTION CIRCUIT FOR TIME MEASUREMENT
    202.
    发明申请
    CHARGE RETENTION CIRCUIT FOR TIME MEASUREMENT 审中-公开
    充电保持电路用于时间测量

    公开(公告)号：WO2008012459A3

    公开(公告)日：2008-03-13

    申请号：PCT/FR2007051696

    申请日：2007-07-20

    Applicant: ST MICROELECTRONICS SA ,  LA ROSA FRANCESCO

    Inventor： LA ROSA FRANCESCO

    IPC: G11C27/02

    CPC classification number: G11C27/005 ,  G04F10/10 ,  G11C27/024

    Abstract: The invention relates to an electronic charge retention circuit for time measurement, comprising: at least a first capacitive element (C1), a first electrode (21) of which is connected to a floating node (F); at least a second capacitive element (C2), a first electrode (31) of which is connected to said floating node (F), the first capacitive element having a leakage through its dielectric space (23) and the second capacitive element having a capacitance greater than the first; and at least a first transistor (5) having an isolated control terminal connected to said floating node.

    Abstract translation: 本发明涉及一种用于时间测量的电子电荷保持电路，包括：至少第一电容元件（C1），其第一电极（21）连接到浮动节点（F）; 至少第二电容元件（C2），其第一电极（31）连接到所述浮动节点（F），所述第一电容元件通过其介电空间（23）具有泄漏，所述第二电容元件具有电容 大于第一; 以及具有连接到所述浮动节点的隔离控制端的至少第一晶体管（5）。

    INTEGRATED CIRCUIT COMPRISING A SECURE TEST MODE USING INTEGRATED CIRCUIT CONFIGURABLE CELL CHAIN STATUS DETECTION
    203.
    发明申请
    INTEGRATED CIRCUIT COMPRISING A SECURE TEST MODE USING INTEGRATED CIRCUIT CONFIGURABLE CELL CHAIN STATUS DETECTION 审中-公开
    使用集成电路配置小区链状态检测的包含安全测试模式的集成电路

    公开(公告)号：WO2006120315A8

    公开(公告)日：2007-12-06

    申请号：PCT/FR2006000901

    申请日：2006-04-21

    Applicant: ST MICROELECTRONICS SA ,  BANCEL FREDERIC ,  HELY DAVID

    Inventor： BANCEL FREDERIC ,  HELY DAVID

    IPC: G01R31/317 ,  G01R31/3185

    CPC classification number: G01R31/318536 ,  G01R31/31719

    Abstract: The invention relates to an electronic circuit including a plurality of configurable cells (2a, ..., 2Y, 2z) configured by a control circuit such as an access controller (CTAP) when it receives a mode control signal (TEST_MODE): either in a functional condition in which the configurable cells are operably connected to logic cells (10 to 15) with which they cooperate to form at least one logic circuit, when the mode control signal is in a first (inoperative) condition, or in a chained condition in which the configurable cells are operably connected in a chain to form a shift register, when the mode control signal is in a second (operative) condition. The circuit as per the invention further includes a detection circuit for generating an operative condition signal (ETAT) if a chained condition is detected in the configurable cells when the control circuit receives the mode control signal in the first condition.

    Abstract translation: 本发明涉及一种电子电路，包括当接收到模式控制信号（TEST_MODE）时由诸如访问控制器（CTAP）的控制电路配置的多个可配置单元（2a，...，2Y，2z）： 功能条件，其中当模式控制信号处于第一（不工作）状态或处于链状态时，可配置单元可操作地连接到逻辑单元（10至15），与逻辑单元协作以形成至少一个逻辑电路 其中当模式控制信号处于第二（可操作）状态时，其中可配置单元可操作地连接在链中以形成移位寄存器。 根据本发明的电路还包括检测电路，用于在控制电路在第一状态下接收模式控制信号时在可配置单元中检测到链接条件时产生操作状态信号（ETAT）。

    METHOD AND CIRCUIT FOR LOCAL CLOCK GENERATION AND SMARTCARD INCLUDING IT THEREON
    204.
    发明申请
    METHOD AND CIRCUIT FOR LOCAL CLOCK GENERATION AND SMARTCARD INCLUDING IT THEREON 审中-公开
    用于本地时钟产生的方法和电路以及包括它的智能卡

    公开(公告)号：WO2007042928A2

    公开(公告)日：2007-04-19

    申请号：PCT/IB2006002860

    申请日：2006-10-06

    Applicant: AXALTO SA ,  ST MICROELECTRONICS SA ,  LEYDIER ROBERT ,  POMET ALAIN ,  DUVAL BENJAMIN

    Inventor： LEYDIER ROBERT ,  POMET ALAIN ,  DUVAL BENJAMIN

    IPC: G06F1/04 ,  H03L7/197

    CPC classification number: G06F1/04 ,  H03K5/133 ,  H03K5/135 ,  H03K5/156 ,  H03K2005/00058 ,  H04L7/0338

    Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal f(0) to f(2 i -1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal f(0) to j(2 i -1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal f(0) to f(2 i -1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

    Abstract translation: 一个延迟电路插入时钟恢复电路内的开环，以提高时钟恢复的精度。 一个振荡器信号f（0）至f（2-i-1）被提供有基本的时间步长。 在接收到的比特流内测量与比特持续时间相对应的时间步长的合理数量。 振荡器信号f（0）至j（2≤I-1）被变换成具有与所述时钟信号的有效边沿同时具有至少一个振荡器信号f（0）至f （2 i），两个连续的有效边缘被分离成与时间步长数的整数部分成比例的时间长度。 计算时间延迟与时间步长数的小数部分成比例。 时钟信号CK的下一个有效沿延迟所述计算的延迟。

    IMAGE SENSOR
    205.
    发明申请
    IMAGE SENSOR 审中-公开
    图像传感器

    公开(公告)号：WO2005050741A3

    公开(公告)日：2005-07-28

    申请号：PCT/FR2004050585

    申请日：2004-11-12

    Applicant: ST MICROELECTRONICS SA ,  VAILLANT JEROME

    Inventor： VAILLANT JEROME

    IPC: H01L27/146 ,  H01L31/0232

    CPC classification number: H01L27/14627 ,  H01L27/14601 ,  H01L27/14643

    Abstract: The invention relates to an image sensor comprising: a substrate (13); transparent layers (18) which cover the substrate and which define a face (28) that is exposed to light; different photosensitive zones (14, 16) at the substrate; and, for each photosensitive zone, a first optical means (29, 30) which is designed to deflect the light reaching a central area of a portion of the exposed face in the direction of the photosensitive zone. The inventive sensor also comprises, for each photosensitive zone, a second optical means (46, 48) which is different from the first and which is designed to deflect the light reaching a peripheral area (36) of said portion of the exposed face in the direction of the photosensitive zone, said peripheral area surrounding the aforementioned central area.

    Abstract translation: 本发明涉及一种图像传感器，包括：衬底（13）; 透明层（18），所述透明层（18）覆盖所述基底并且限定暴露于光的面（28）; 在衬底上的不同的光敏区（14,16） 并且对于每个光敏区域设置第一光学装置（29,30），该第一光学装置被设计成使光线在光敏区域的方向上偏转到达暴露面的一部分的中心区域。 对于每个光敏区域，本发明的传感器还包括与第一光学装置不同的第二光学装置（46,48），并且该第二光学装置被设计成将到达所述曝光面的所述部分的外围区域（36）的光偏转 光敏区的方向，所述周边区域围绕前述中心区域。

    RING LOCATION
    207.
    发明申请
    RING LOCATION 审中-公开
    环位置

    公开(公告)号：WO03025841B1

    公开(公告)日：2003-10-09

    申请号：PCT/FR0203136

    申请日：2002-09-13

    Applicant: ST MICROELECTRONICS SA ,  TISSE CHRISTEL-LOIC

    Inventor： TISSE CHRISTEL-LOIC

    IPC: G06K9/00 ,  G06K9/46 ,  G06T7/00 ,  G06T7/60

    CPC classification number: G06K9/00604 ,  G06K9/00268 ,  G06K9/4633 ,  G06T7/66 ,  G06T7/70 ,  G06T2207/30041

    Abstract: The invention concerns a method for locating, in a digital image, a circle centre, comprising the following steps: a) predefining a set of potential radii of the circle; b) dimensioning (303) two accumulators to a dimension in the form of a column matrix not larger than the size of the image in x-axis and a line matrix not larger than the size of the image in y-axis; c) sequentially, for each pixel of the image: (i) selecting successively each potential radius; (ii) evaluating the position of the potential centre of a circle of the selected radius and whereof the pixel concerned is on the periphery; and (iii) incrementing said accumulators at the x-axis and the y-axis of the potential centre; and d) selecting (304), as coordinates of the located centre, the x-axis and the y-axis corresponding to the maximum of accumulators.

    Abstract translation: 本发明涉及一种用于在数字图像中定位圆心的方法，包括以下步骤：a）预定义一组圆的潜在半径; b）将两个累加器的尺寸（303）设为不大于x轴中的图像尺寸的列矩阵形式的尺寸和不大于y轴中图像尺寸的线矩阵; c）顺序地，对于图像的每个像素：（i）连续地选择每个电位半径; （ii）评估所选半径的圆的潜在中心的位置，并且其相关像素在其周边上; 和（iii）在电位中心的x轴和y轴处增加所述累加器; 以及d）选择（304）作为定位中心的坐标，与累加器的最大值相对应的x轴和y轴。

    INTEGRATED CIRCUIT WITH DRAM MEMORY CELL
    208.
    发明申请
    INTEGRATED CIRCUIT WITH DRAM MEMORY CELL 审中-公开
    集成电路与DRAM存储器单元

    公开(公告)号：WO03017362A8

    公开(公告)日：2003-04-03

    申请号：PCT/FR0202887

    申请日：2002-08-14

    Applicant: ST MICROELECTRONICS SA ,  MAZOYER PASCALE ,  CAILLAT CHRISTIAN

    Inventor： MAZOYER PASCALE ,  CAILLAT CHRISTIAN

    IPC: H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10852 ,  H01L27/10888

    Abstract: The invention concerns an integrated circuit comprising a substrate (1), at least a capacitor (9) arranged above the substrate (1) and provided with a first electrode (5), a second electrode (8), and a dielectric (7) arranged between the two electrodes, at least a connecting feedthrough between the substrate (1) and a conductive level located above the capacitor (9), and a dielectric material covering the substrate (1) and enclosing the capacitor (9) and the feedthrough. The feedthrough comprises a first portion (18) arranged between the substrate and the lower level of the first electrode, a second portion (6) arranged between the lower level of the first electrode and the upper level of the first electrode, and a third portion (12) in contact with the first electrode and flush with said conductive level, the second portion being made of the same material as the first electrode of the capacitor.

    Abstract translation: 本发明涉及一种集成电路，该集成电路包括衬底（1），布置在衬底（1）上方并且设置有第一电极（5），第二电极（8）和电介质（7）的至少一个电容器（9） 布置在所述两个电极之间，所述衬底（1）和位于所述电容器（9）上方的导电层之间的至少一个连接馈通，以及覆盖所述衬底（1）并封闭所述电容器（9）和所述馈通的介电材料。 馈通包括布置在基板与第一电极的下层之间的第一部分（18），布置在第一电极的下层与第一电极的上层之间的第二部分（6），以及第三部分 （12）与所述第一电极接触并与所述导电层平齐，所述第二部分由与所述电容器的第一电极相同的材料制成。

    SENSOR SEMICONDUCTOR PACKAGE, PROVIDED WITH AN INSERT, AND METHOD FOR MAKING SAME
    210.
    发明申请
    SENSOR SEMICONDUCTOR PACKAGE, PROVIDED WITH AN INSERT, AND METHOD FOR MAKING SAME 审中-公开
    传感器半导体封装，提供插件及其制造方法

    公开(公告)号：WO02056388A3

    公开(公告)日：2003-01-03

    申请号：PCT/FR0200069

    申请日：2002-01-10

    Applicant: ST MICROELECTRONICS SA ,  PRIOR CHRISTOPHE

    Inventor： PRIOR CHRISTOPHE

    IPC: H01L21/56 ,  H01L31/0203 ,  H01L31/0232

    CPC classification number: H01L31/0203 ,  H01L21/565 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/1815 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: The invention concerns a semiconductor package and its production method, wherein a semiconductor component (5) is fixed on a front surface of mounting and electrical connection means (2) and comprising a sensor (8), an insert (11) being supported on the front surface of said optical component, around said sensor and comprising an open passage (14) extending in front of said sensor, and encapsulating means (26) comprising a coating material which encloses said semiconductor component and the mounting and electrical connecting means, said passage comprising a cap (17).

    Abstract translation: 本发明涉及一种半导体封装及其制造方法，其中半导体部件（5）固定在安装和电气连接装置（2）的前表面上并且包括传感器（8），插入件（11）被支撑在 所述光学部件的前表面围绕所述传感器并且包括在所述传感器的前面延伸的开放通道（14），以及封装装置（26），其包括封装所述半导体部件和所述安装和电连接装置的所述通道 包括盖（17）。

Patent Agency Ranking