公开(公告)号：WO2005033683A1

公开(公告)日：2005-04-14

申请号：PCT/IT2004/000555

申请日：2004-10-06

Applicant: STMICROELECTRONICS S.R.L. ,  ALBERICI, Stefano, Giovanni

Inventor： ALBERICI, Stefano, Giovanni

IPC: G01N23/227

CPC classification number: H01J37/256 ,  G01N23/227 ,  H01J37/05 ,  H01J2237/053 ,  H01J2237/057 ,  H01J2237/06316 ,  H01J2237/24571 ,  H01J2237/2511 ,  H01J2237/2561

Abstract: An electroscope system based on exciting a certain area of the surface of a sample to emit electrons with a characteristic distribution of kinetic energies, has the analyzed area of the sample excited by an electron beam produced by a field emission source and a monochromator energy filter of said electron beam disposed down-stream of the electron source.The field emission electron source is preferably a Schottky source and monochromator energy filter reduces energy dispertion of the electrons of said electron beam to less than 0.2 eV. Microareas of linear dimensions in the order of ten nm may be analyzed while observing them gathering information on the chemical state of detected elements present at the surface of the examined microarea of the sample.

Abstract translation: 基于激发样品表面的特定区域以发射具有动能特征分布的电子的电镜系统，具有由场发射源产生的电子束和由单个器能量滤波器产生的电子束激发的样本的分析面积 所述电子束设置在电子源的下游。场发射电子源优选为肖特基源，并且单色器能量滤波器将所述电子束的电子的能量差异减小到小于0.2eV。 可以分析十纳米级的线性尺寸的微孔，同时观察它们收集关于存在于检测到的微区表面上的检测元素的化学状态的信息。

公开(公告)号：WO2003073509A1

公开(公告)日：2003-09-04

申请号：PCT/IT2002/000123

申请日：2002-02-28

Applicant: STMICROELECTRONICS S.R.L. ,  RONSISVALLE, Cesare

Inventor： RONSISVALLE, Cesare

IPC: H01L27/07

CPC classification number: H01L27/0825 ,  H01L21/8222 ,  H01L27/0744

Abstract: The invention relates to an improved bipolar transistor structure (1) that may be integrated into a Darlington configuration, of the type having conventional base (B), collector (C) and emitter (E) terminals and comprising a resistance (R) between the collector (C) and the (B) and a thyristor device (3) SCR between the base (B) and the emitter (E). The resistance (R) is a high voltage resistance to keep normally ON the transistor structure while the thyristor is a turning off circuit that is enabled and driven on its gate terminal.

Abstract translation: 本发明涉及一种改进的双极晶体管结构（1），其可以集成到具有常规基极（B），集电极（C）和发射极（E）端子的类型的达林顿配置中，并且包括在 集电极（C）和（B）以及晶闸管器件（3）在基极（B）和发射极（E）之间的SCR。 电阻（R）是高电压电阻，以保持晶体管结构的正常导通，而晶闸管是在其栅极端子上使能和驱动的关断电路。

公开(公告)号：WO2020053700A1

公开(公告)日：2020-03-19

申请号：PCT/IB2019/057382

申请日：2019-09-02

Applicant: STMICROELECTRONICS S.R.L.

Inventor： GUERRIERI, Lorenzo ,  POLONI, Angelo ,  LAURI, Edoardo

IPC: H04W4/20 ,  H04L29/08

Abstract: A method of communication for use, for instance, in systems such as solar panel power generation systems, house monitoring systems, traffic surveillance systems or smart street lighting systems may comprise:- providing a communication circuit (such as a modem 10) for communicating signals conveying information messages, the communication circuit (10) supporting a first communication protocol (101), adopting, for instance, S-FSK modulation, and a second communication protocol (102), adopting, for instance,PSK or QAM modulation,- including in the communicated signals first signals conveying first information messages and second signals conveying second information messages, wherein the first information messages comprise repetitive messages having fixed repeated content and the second information messages comprise non-repetitive messages having variable content, and- transmitting the first signals and the second signals via the communication circuit using the first communication protocol (101) for the first, repetitive signals and the second communication protocol (102) for the second, non-repetitive signals, respectively.

公开(公告)号：WO2015055728A1

公开(公告)日：2015-04-23

申请号：PCT/EP2014/072139

申请日：2014-10-15

Applicant: STMICROELECTRONICS (GRENOBLE2) SAS ,  STMICROELECTRONICS S.R.L

Inventor： SOULIE, Michael ,  LOCATELLI, Riccardo ,  CATALANO, Valerio ,  MARUCCIA, Giuseppe ,  GUARNACCIA, Giuseppe ,  GUARRASI, Raffaele

IPC: G06F13/16 ,  G06F12/06

CPC classification number: G06F12/0607 ,  G06F13/1647 ,  G06F15/7825 ,  G06F17/5077 ,  G06F2212/656

Abstract: A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.

Abstract translation: 一种方法，包括：接收与地址相关联并具有交易目的地的交易，所述地址在存储器的交织区域中; 确定所述交易的多个目的地中的一个，所述交织的存储器区域的不同部分可分别由所述多个目的地可访问; 以及将路由信息与所述事务相关联，所述路由信息与所确定的目的地相关联。

公开(公告)号：WO2013030798A1

公开(公告)日：2013-03-07

申请号：PCT/IB2012/054497

申请日：2012-08-31

Applicant: STMicroelectronics S.r.l. ,  POLITECNICO DI MILANO ,  COMI, Claudia ,  CORIGLIANO, Alberto ,  ZERBINI, Sarah

Inventor： COMI, Claudia ,  CORIGLIANO, Alberto ,  ZERBINI, Sarah

IPC: G01P15/097

CPC classification number: G01P15/0975 ,  G01P15/097

Abstract: A detection, structure (1) for a z-axis resonant accelerometer (24) is provided with an inertial mass (2) anchored to a substrate (20) by means of elastic anchorage elements (6) so as to be suspended above the substrate (20) and perform an inertial movement of rotation about a first axis of rotation (A) belonging to a plane (xy) of main extension of the inertial mass (2), in response to an external acceleration (a-) acting along a vertical axis (z) transverse with respect to the plane (xy); and a first resonator element (10a) and a second resonator element (10b), which are mechanically coupled to the inertial mass (2) by respective elastic supporting elements (16), which enable a movement of rotation about a second axis of rotation (B) and a third axis of rotation (C), in a resonance condition. In particular, the second axis of rotation (B) and the third axis of rotation (C) are parallel to one another, and are moreover parallel to the first axis of rotation (A) of the inertial mass (2).

Abstract translation: 用于z轴共振加速度计（24）的检测结构（1）具有通过弹性锚定元件（6）锚定到基底（20）上的惯性质量块（2），以悬浮在基底上方 （20），并且响应于沿着惯性质量（2）的主延伸的平面（xy）的旋转的第一旋转轴线（A），沿着沿着惯性质量 垂直轴（z）相对于平面（xy）横向; 以及通过相应的弹性支撑元件（16）机械耦合到惯性块（2）的第一谐振器元件（10a）和第二谐振元件（10b），其使得能够围绕第二旋转轴线旋转 B）和第三旋转轴（C）。 特别地，第二旋转轴线（B）和第三旋转轴线（C）彼此平行，并且平行于惯性质量块（2）的第一旋转轴线（A）。

公开(公告)号：WO2012085951A1

公开(公告)日：2012-06-28

申请号：PCT/IT2010/000511

申请日：2010-12-23

Applicant: STMICROELECTRONICS S.R.L. ,  BOTTAREL, Valeria ,  RICOTTI, Giulio ,  QUAGLIA, Fabio

Inventor： BOTTAREL, Valeria ,  RICOTTI, Giulio ,  QUAGLIA, Fabio

IPC: H03K17/081 ,  H03K17/30 ,  G01S7/52 ,  B06B1/02

CPC classification number: H03K17/16 ,  H03K17/08104 ,  H03K17/30

Abstract: A low voltage isolation circuit (1) is described inserted between a connection node (HVout) to a matrix (2) of switches suitable for receiving a high voltage signal (IM) and a connection terminal (pzt) to a load (PZ) suitable for transmitting said high voltage signal (IM) to said load (PZ) of the type comprising at least one driving block (5) inserted between a first and a second voltage reference (Vss, - Vss) and comprising at least a first driving transistor (M l), inserted, in series with a first driving diode (Dl), between the first voltage reference (Vss) and a first driving central circuit node (Xc) and a second driving transistor (M2), in turn inserted, in series with a second diode (D2), between the driving central circuit node (Xc) and the second supply voltage reference (-Vss). The switch comprises an isolation block (8) connected to the connection terminal (pzt), to the connection node (HVout) and to the driving central circuit node (Xc) and comprising at least one voltage limiter block (6), a diode block (7) and a control transistor (MD), in turn connected across the diode block (7) between the connection node (HVout) to the matrix (2) of switches and the connection terminal (pzt) to the load (PZ) of the low voltage isolation switch (1) and having a control terminal (XD) connected to the driving central circuit node (Xc).

Abstract translation: 描述了一种低电压隔离电路（1），其插入到适于接收高电压信号（IM）的开关的矩阵（2）的连接节点（HVout）和适合于负载（PZ）的连接端子（pzt）之间 用于将所述高电压信号（IM）发送到包括插入在第一和第二参考电压（Vss，-Vss）之间的至少一个驱动块（5）的类型的所述负载（PZ），并且至少包括第一驱动晶体管 （M1）与第一驱动二极管（D1）串联插入在第一电压基准（Vss）和第一驱动中心电路节点（Xc）和第二驱动晶体管（M2）之间，然后插入 与驱动中心电路节点（Xc）和第二电源电压基准（-Vss）之间的第二二极管（D2）串联。 开关包括连接到连接端子（pzt）的隔离块（8），连接节点（HVout）和驱动中心电路节点（Xc），并且包括至少一个限压器块（6），二极管块 （7）和控制晶体管（MD），它们连接在连接节点（HVout）与开关矩阵（2）之间的二极管块（7）和连接端子（pzt）与负载（PZ）之间 低电压隔离开关（1）并具有连接到驱动中心电路节点（Xc）的控制端子（XD）。

公开(公告)号：WO2012085296A1

公开(公告)日：2012-06-28

申请号：PCT/EP2011/074045

申请日：2011-12-23

Applicant: STMICROELECTRONICS S.R.L. ,  PACI, Dario ,  MORELLI, Marco ,  RIVA, Caterina

Inventor： PACI, Dario ,  MORELLI, Marco ,  RIVA, Caterina

IPC: G01R33/00 ,  G01R33/09

CPC classification number: G01R33/0011 ,  B82Y25/00 ,  G01R33/093 ,  H01L43/12

Abstract: An integrated magnetoresistive device, where a substrate (17) of semiconductor material is covered, on a first surface (19), by an insulating layer (18). A magnetoresistor (26) of ferromagnetic material extends in the insulating layer and defines a sensitivity plane of the sensor. A concentrator (34) of ferromagnetic material including at least one arm (34a), extending in a transversal direction to the sensitivity plane and vertically offset to the magnetoresistor (26). In this way, magnetic flux lines directed perpendicularly to the sensitivity plane are concentrated and deflected so as to generate magnetic-field components directed in a parallel direction to the sensitivity plane.

Abstract translation: 通过绝缘层（18）在第一表面（19）上覆盖半导体材料的衬底（17）的集成磁阻器件。 铁磁材料的磁阻（26）在绝缘层中延伸并限定传感器的灵敏度平面。 铁磁材料的集中器（34）包括至少一个臂（34a），沿着横向方向延伸到灵敏度平面并垂直偏移到磁电阻（26）。 以这种方式，垂直于灵敏度平面指向的磁通线被集中和偏转，以便产生指向与灵敏平面平行的方向的磁场分量。

公开(公告)号：WO2012019768A1

公开(公告)日：2012-02-16

申请号：PCT/EP2011/004030

申请日：2011-08-11

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto ,  GIRLANDO, Giovanni

Inventor： PAGANI, Alberto ,  GIRLANDO, Giovanni

IPC: G06K19/073

CPC classification number: G06K7/00 ,  G06K7/10178 ,  G06K19/025 ,  G06K19/072 ,  G06K19/07327 ,  G06K19/07336 ,  G06K19/07735 ,  G06K19/07756 ,  G06K19/07771 ,  G06K19/07775 ,  G06K19/07779

Abstract: The invention relates to a security system comprising at least one integrated circuit (24a) and a transceiver / transponder circuit (30), the at least one integrated circuit (24a) being provided with an antenna (36) for communicating with the transceiver / transponder circuit (30), an inhibiting element (24b, 44, 44a, 44b) being associated with the at least one integrated circuit (24a) for inhibiting communications with the transceiver / transponder circuit (30) and for securing the data contained in the at least one integrated circuit (24a). Advantageously, the inhibiting element (24b, 44, 44a, 44b) is an electromagnetic inhibiting element, the security system further comprising a coupling element (22) that is associated with the antenna (36) of the at least one integrated circuit (24a) for temporarily deactivating the electromagnetic inhibiting element (24b, 44, 44a, 44b) to allow communications between the at least one integrated circuit (24a) and the transceiver / transponder circuit (30).

Abstract translation: 本发明涉及一种包括至少一个集成电路（24a）和收发器/应答器电路（30）的安全系统，所述至少一个集成电路（24a）设置有天线（36），用于与收发器/应答器 电路（30），与所述至少一个集成电路（24a）相关联的禁止元件（24b，44,44a，44b），用于禁止与所述收发器/应答器电路（30）的通信并且用于保护包含在所述收发器/ 至少一个集成电路（24a）。 有利地，禁止元件（24b,44,44a，44b）是电磁抑制元件，所述安全系统还包括与所述至少一个集成电路（24a）的天线（36）相关联的耦合元件（22） 用于临时停用所述电磁抑制元件（24b,44,44a，44b）以允许所述至少一个集成电路（24a）与所述收发器/应答器电路（30）之间的通信。

公开(公告)号：WO2011088853A1

公开(公告)日：2011-07-28

申请号：PCT/EP2010/005927

申请日：2010-09-29

Applicant: STMICROELECTRONICS S.R.L. ,  ROSSI, Sandro ,  RICOTTI, Giulio ,  GHISU Davide Ugo ,  RICCIARDO, Antonio

Inventor： ROSSI, Sandro ,  RICOTTI, Giulio ,  GHISU Davide Ugo ,  RICCIARDO, Antonio

IPC: H03K17/06 ,  H03K17/687 ,  H03K17/74 ,  B06B1/02 ,  H03K17/0416 ,  H03K17/16

CPC classification number: H03K17/06 ,  H03K17/04163 ,  H03K17/161 ,  H03K17/6872 ,  H03K17/74

Abstract: A transmission channel (1) is described comprising at least one high voltage buffer block (4) comprising buffer transistors (MB1, MB2, MB3, MB4) and respective buffer diodes (DB1, DB2, DB3, DB4), being inserted between respective voltage references (HVP0, HVP1, HVM0, HVM1), a clamping circuit (10) being connected to a first output terminal (HVout) of the transmission channel (1), an antinoise block (6) being connected between the first output terminal (HVout) and a connection terminal (Xdcr) of the transmission channel (1); as well as a switching circuit (30) being inserted between the connection terminal (Xdcr) and a second output terminal (LVout) of the transmission channel (1). Advantageously according to the invention, the clamping circuit (10) comprises a clamping core (11), a reset circuit (20) comprising diodes (DME1, DME2, DME3, DME4 ) inserted between circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2) of the high voltage buffer block (4) and of the clamping circuit (10), the circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2 ) being in correspondance with conduction terminals of said transistors (MB1,MB2,MB3,MB4,MC1,MC2) comprised into the high voltage buffer block(4) and into the clamping circuit (10), and a switching circuit (30).

Abstract translation: 描述了传输通道（1），其包括至少一个包括缓冲晶体管（MB1，MB2，MB3，MB4）和相应的缓冲二极管（DB1，DB2，DB3，DB4）的高压缓冲块（4） 参考（HVP0，HVP1，HVM0，HVM1），与传输通道（1）的第一输出端子（HVout）连接的钳位电路（10），连接在第一输出端子 ）和传输信道（1）的连接终端（Xdcr）; 以及插入在传输通道（1）的连接端子（Xdcr）和第二输出端子（LVout）之间的开关电路（30）。 有利地，根据本发明，夹紧电路（10）包括夹紧芯（11），复位电路（20），其包括插入在电路节点（XME1，XME2，XME3，XME4，XME3，DME3， 高电压缓冲块（4）和钳位电路（10）的电路节点（XME1，XME2，XME3，XME4，XC1，XC2）与所述晶体管（MB1，XC1，XC2）的导通端子相对应， MB2，MB3，MB4，MC1，MC2）以及开关电路（30），其特征在于，包括高压缓冲块（4）和钳位电路（10）。

公开(公告)号：WO2011079879A1

公开(公告)日：2011-07-07

申请号：PCT/EP2010/005926

申请日：2010-09-29

Applicant: STMICROELECTRONICS S.R.L. ,  BOTTAREL, Valeria ,  RICOTTI, Giulio ,  MARABELLI, Silvia

Inventor： BOTTAREL, Valeria ,  RICOTTI, Giulio ,  MARABELLI, Silvia

IPC: H03K17/693 ,  H03K17/74 ,  H03K17/687 ,  H03K17/06 ,  B06B1/02 ,  H03K17/0812 ,  H03K17/0814

CPC classification number: H03K17/693 ,  B06B1/0215 ,  H03K17/06 ,  H03K17/08122 ,  H03K17/08142 ,  H03K17/6872 ,  H03K17/74

Abstract: A low voltage isolation circuit (1) is described inserted between an input terminal (HVout) suitable for receiving a high voltage signal (IM) and an output terminal (pzt) suitable for transmitting the high voltage signal (IM) to a load (PZ) of the type comprising at least one driving block (5) inserted between a first and a second voltage reference (Vss, -Vss) and comprising a first driving transistor (Ml), inserted between the first voltage reference (Vss) and a first driving central circuit node (Xc) and a second driving transistor (M2), in turn inserted between the driving central circuit node (Xc) and the second supply voltage reference (-Vss) as well as an isolation block (8) connected to the connection terminal (pzt), to the input terminal (HVout) and, through a protection block (9) comprising a first and a second protection transistor (MD1, MD2), being in anti-series to each other and having control terminals receiving respective complementary protection driving signals (dr1, dr2), to the driving central circuit node (Xc), the isolation block (8) comprising at least one voltage limiter block (6), a diode block (7) and a control transistor (MD), in turn connected across the diode block (7) between the input (HVout) and output (pzt) terminals of the low voltage isolation switch (1) and having a control terminal (XD) connected to the driving central circuit node (Xc) through the protection block (9), said diode block (7) comprising at least one first and one second transmission diode (DN1, DN2), connected in antiparallel, i.e. by having an anode terminal of said first diode connected to a cathode terminal of said second diode and vice versa.

Abstract translation: 描述了一种低压隔离电路（1），其插入适于接收高电压信号（IM）的输入端（HVout）和适于将高电压信号（IM）发送到负载（PZ）的输出端（pzt）之间 ）包括插入在第一和第二电压参考（Vss，-Vss）之间的至少一个驱动块（5），并且包括插入在第一电压参考（Vss）和第一电压参考（Vss）之间的第一驱动晶体管（M1） 驱动中心电路节点（Xc）和第二驱动晶体管（M2），其又插入在驱动中心电路节点（Xc）和第二电源电压参考（-Vss）之间，以及隔离块（8） 连接端子（pzt）到输入端子（HVout），并且通过包括第一和第二保护晶体管（MD1，MD2）的保护块（9）彼此反串联并且具有相应的控制端子 互补保护驾驶信号（dr1，dr 如图2所示，驱动中心电路节点（Xc），隔离块（8）包括至少一个限压器块（6），二极管块（7）和控制晶体管（MD） 在低压隔离开关（1）的输入（HVout）端子和输出端子（pzt）端子之间具有通过保护块（9）连接到驱动中心电路节点（Xc）的控制端子（XD）的块（7） ，所述二极管块（7）包括至少一个反并联连接的第一和第二传输二极管（DN1，DN2），即通过使所述第一二极管的阳极端子连接到所述第二二极管的阴极端子，反之亦然。