公开(公告)号：EP1126611A1

公开(公告)日：2001-08-22

申请号：EP01300962.6

申请日：2001-02-02

Applicant: STMicroelectronics Limited

Inventor： Darzy, Saul

IPC: H03K19/00 ,  H03K19/017 ,  H03K19/003

CPC classification number: H03K19/00361 ,  H03K19/0013 ,  H03K19/00315

Abstract: A circuit for providing a control signal for a load includes a first switch having a first and a second state, a second switch having a first and a second state coupled to said first switch, a load connected to said first and second switches, protection circuitry for protecting said load from excessive voltage and circuitry for switching said first switch. The circuit is arranged so that when the first switch is in the first state current flows from the load to the first switch and the switching circuitry is arranged to switch the first switch to the second state when the voltage across the load reaches a predetermined value.

Abstract translation: 用于为负载提供控制信号的电路包括具有第一和第二状态的第一开关，具有耦合到所述第一开关的第一和第二状态的第二开关，连接到所述第一和第二开关的负载，保护电路 用于保护所述负载免受过度电压和用于切换所述第一开关的电路。 电路布置成使得当第一开关处于第一状态时，电流从负载流向第一开关，并且开关电路被布置成当跨过负载的电压达到预定值时将第一开关切换到第二状态。

公开(公告)号：EP1119003A2

公开(公告)日：2001-07-25

申请号：EP00309493.5

申请日：2000-10-27

Applicant: STMicroelectronics Limited

Inventor： Raymond, Paul

IPC: G11C8/00

CPC classification number: H03M7/16 ,  G11C5/063 ,  G11C8/00 ,  G11C8/10

Abstract: An method of arranging address decoders in an improved manner in an integrated circuit memory is discussed. In the integrated circuit memory the address lines extending from the address circuitry of the integrated circuit memory are connected to address decoders, each word line of the memory being connected to an address decoder. The address decoders are connected to the address lines in a certain combination such that only one f the address lines is connected to adjacent address decoders.
When connected in this manner the average propagation delay of each address line is substantially uniform. By reducing the maximum propagation delay in comparison with previously known arrangements of address decoders the speed at which the memory can be operated is increased.

Abstract translation: 讨论了在集成电路存储器中以改进的方式布置地址解码器的方法。 在集成电路存储器中，从集成电路存储器的地址电路延伸的地址线连接到地址解码器，存储器的每个字线连接到地址解码器。 地址解码器以某种组合连接到地址线，使得只有一个地址线连接到相邻的地址解码器。 当以这种方式连接时，每条地址线的平均传播延迟基本上是一致的。 与先前已知的地址解码器配置相比，通过减小最大传播延迟，存储器可以被操作的速度增加。

公开(公告)号：EP1096398A1

公开(公告)日：2001-05-02

申请号：EP00309177.4

申请日：2000-10-18

Applicant: STMicroelectronics Limited

Inventor： Ballam, Peter

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A method is described for verifying the output from an analogue simulation model of a hardware circuit. The method comprises the steps of stimulating the analogue model by applying a preselected voltage to an input pin of the analogue model, driving one or more selected output pins of the analogue model with a test voltage having a selected drive strength different from an expected output drive strength, measuring the output voltage of each output pin, comparing the measured output voltage and the expected output voltage and responsive to said comparison, providing a verifying output if the measured and expected voltages are not in contradiction.

Abstract translation: 描述了一种用于验证来自硬件电路的模拟仿真模型的输出的方法。 该方法包括以下步骤：通过将预选电压施加到模拟模型的输入引脚来刺激模拟模型，用具有与预期输出驱动器不同的选定驱动强度的测试电压驱动模拟模型的一个或多个选定的输出引脚 测量每个输出引脚的输出电压，比较测量的输出电压和预期的输出电压，并响应于所述比较，提供验证输出，如果测量的和预期的电压不是矛盾的。

公开(公告)号：EP1085412A2

公开(公告)日：2001-03-21

申请号：EP00307580.1

申请日：2000-09-01

Applicant: STMicroelectronics Limited

Inventor： Shann, Richard

IPC: G06F9/445

CPC classification number: G06F8/54

Abstract: An executable program is prepared from a plurality of object code modules, each module including relocation instructions having an instruction format which includes a classification field for holding a relocation class indicator and a set of relocation fields for holding relocation data. The meaning of the relocation data depends on the class indicator. The instruction format is common to first and second classes of relocations. The executable program is prepared by reading the relocation instructions and determining from the relocation class indicator the class of the relocation instruction and executing the relocation operations on section data in dependence on the class of relocation instruction indicated by the relocation class indicator.
A linker is provided for preparing the executable program from object code modules containing the relocation instructions. A computer program may be provided to control the linker.

Abstract translation: 从多个目标代码模块准备可执行程序，每个模块包括具有指令格式的重定位指令，该指令格式包括用于保存重定位类别指示符的分类字段和用于保存重定位数据的重定位字段集合。 重定位数据的含义取决于类指标。 指令格式对于第一类和第二类重定位是通用的。 通过读取重定位指令并根据重定位类指示符确定重定位指令的类并根据重定位类指示符指示的重定位指令的类执行对部分数据的重定位操作来准备可执行程序。 提供了一个链接器，用于从包含重定位指令的目标代码模块中准备可执行程序。 可以提供计算机程序来控制链接器。

公开(公告)号：EP1083659A1

公开(公告)日：2001-03-14

申请号：EP00307665.0

申请日：2000-09-05

Applicant: STMicroelectronics Limited

Inventor： Barnes, William Bryan

IPC: H03K19/003 ,  H03K19/00 ,  H03K19/0185

CPC classification number: H03K19/018521

Abstract: A level shifter uses a current mirror as a current switch connected to the drains of two oppositely-driven FETs. A switch selectively connects the current mirror to its power supply so that no quiescent DC current flows.

Abstract translation: 电平转换器使用电流镜作为连接到两个相对驱动的FET的漏极的电流开关。 开关选择性地将电流镜连接到其电源，使得没有静态DC电流流动。

公开(公告)号：EP1061528A1

公开(公告)日：2000-12-20

申请号：EP00302825.5

申请日：2000-04-04

Applicant: STMicroelectronics Limited

Inventor： Nurser, Henry, c/o Stmicroelectronics Limited

IPC: G11C29/00

CPC classification number: G11C29/028 ,  G11C11/41 ,  G11C29/50 ,  G11C29/50012

Abstract: An apparatus and method for determining the minimum clock delay first of all determines the response time of the overall circuit by varying the application instant of an external clock until the circuit output is just valid. Then an external senseamp clock is substituted for the internal senseamp clock and the instant of application of the external clock is again varied until the circuit output is just valid.

Abstract translation: 首先确定最小时钟延迟的装置和方法首先通过改变外部时钟的应用时刻来确定整个电路的响应时间直到电路输出正常。 然后用外部感应时钟代替内部感应时钟，再次改变外部时钟的应用时刻，直到电路输出正常。

公开(公告)号：EP1056192A3

公开(公告)日：2000-12-13

申请号：EP00116212.2

申请日：1996-06-24

Applicant: UNIVERSITY OF BRISTOL ,  STMicroelectronics Limited

Inventor： Beach, Mark Anthony ,  Mattos, Philip Gerad

IPC: H03D3/00

CPC classification number: H03B25/00 ,  H03D3/006

Abstract: A fixed frequency dual downconversion receiver, comprises: an analog first downconversion (10) and IF filter stage (20); means for one-bit coding (24) of the downconverted signal; and means for second downconversion by digital subsampling (26,28). The receiver is particularly suitable for use in GPS applications.

Abstract translation: 一种固定频率双下变频接收机，包括：模拟的第一下变频器（10）和中频滤波器级（20）; 用于下变频信号的一位编码（24）的装置; 和通过数字子采样进行第二次下变频的装置（26,28）。 接收器特别适用于GPS应用。

公开(公告)号：EP0713220B1

公开(公告)日：2000-09-13

申请号：EP95307999.3

申请日：1995-11-09

Applicant: STMicroelectronics Limited

Inventor： McIntyre, David Hugh

IPC: G11C5/14 ,  G05F3/24

CPC classification number: G05F3/247 ,  G11C5/147

公开(公告)号：EP0698890B1

公开(公告)日：2000-07-05

申请号：EP95305705.6

申请日：1995-08-16

Applicant: STMicroelectronics Limited

Inventor： McIntyre, Hugh

IPC: G11C29/00 ,  G11C16/06 ,  G06F11/20

CPC classification number: G11C29/24 ,  G11C29/04 ,  G11C29/52

公开(公告)号：EP0971502A3

公开(公告)日：2000-01-19

申请号：EP99203397.7

申请日：1991-02-20

Applicant: STMicroelectronics Limited

Inventor： Simpson, Robert J.

IPC: H04L1/00 ,  G06F13/42 ,  H04L25/02

CPC classification number: H04L1/0063 ,  H04L1/0057 ,  H04L1/0083 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/033 ,  H04L7/048

Abstract: A communication interface for interconnecting a computer with at least one other device has a link output circuit and a link input circuit. A link output on one device is connected to a link input on another device by a data line 25 and a parallel strobe line 26. Data is transmitted on the data line 25 in serial bit strings forming a succession of tokens of predetermined lengths. Signal transitions are provided on the parallel strobe line 26 where no signal transition occurs on the data line 25. Each token includes a bit indicating the length of the token and a parity bit providing a check on bits in a preceding token.