公开(公告)号：US20240221295A1

公开(公告)日：2024-07-04

申请号：US18436522

申请日：2024-02-08

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Subhajit Dasgupta ,  Srivallaba Mysore ,  Michael J. Norris ,  Vasanth Ranganathan ,  Joydeep Ray

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

Abstract: One embodiment provides for a graphics processing unit comprising a processing cluster to perform multi-rate shading via coarse pixel shading and output shaded coarse pixels for processing by a post-shader pixel processing pipeline.

公开(公告)号：US20240211403A1

公开(公告)日：2024-06-27

申请号：US18086441

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Joydeep Ray ,  Karthik Vaidyanathan ,  Sreedhar Chalasani ,  Eric Liskay ,  Prathamesh Raghunath Shinde ,  Vasanth Ranganathan ,  Michael J. Norris ,  Rajasekhar Pantangi ,  Altug Koker

IPC: G06F12/0837 ,  G06F12/0811

CPC classification number: G06F12/0837 ,  G06F12/0811

Abstract: One embodiment provides a graphics processor comprising memory access circuitry configured to generate a virtual address for pixel data at a pixel coordinate on a surface in memory to facilitate the caching of the pixel data in a cache memory before the actual memory address of the pixel coordinate is able to be determined.

公开(公告)号：US12020135B2

公开(公告)日：2024-06-25

申请号：US17446101

申请日：2021-08-26

Applicant: Intel Corporation

Inventor： Liwei Ma ,  Elmoustapha Ould-Ahmed-Vall ,  Barath Lakshmanan ,  Ben J. Ashbaugh ,  Jingyi Jin ,  Jeremy Bottleson ,  Mike B. Macpherson ,  Kevin Nealis ,  Dhawal Srivastava ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman ,  Altug Koker ,  Abhishek R. Appu

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/082 ,  G06T1/20 ,  G06N3/044 ,  G06N3/045

CPC classification number: G06N3/04 ,  G06N3/063 ,  G06N3/082 ,  G06T1/20 ,  G06N3/044 ,  G06N3/045

Abstract: A library of machine learning primitives is provided to optimize a machine learning model to improve the efficiency of inference operations. In one embodiment a trained convolutional neural network (CNN) model is processed into a trained CNN model via pruning, convolution window optimization, and quantization.

公开(公告)号：US12013808B2

公开(公告)日：2024-06-18

申请号：US17429873

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Altug Koker ,  Ben Ashbaugh ,  Scott Janus ,  Aravindh Anantaraman ,  Abhishek R. Appu ,  Niranjan Cooray ,  Varghese George ,  Arthur Hunter ,  Brent E. Insko ,  Elmoustapha Ould-Ahmed-Vall ,  Selvakumar Panneer ,  Vasanth Ranganathan ,  Joydeep Ray ,  Kamal Sinha ,  Lakshminarayanan Striramassarma ,  Prasoonkumar Surti ,  Saurabh Tangri

IPC: G06F13/38 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Embodiments are generally directed to a multi-tile architecture for graphics operations. An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.

公开(公告)号：US12007824B2

公开(公告)日：2024-06-11

申请号：US17517090

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Altug Koker ,  Abhishek R. Appu ,  Bhushan M. Borole ,  Wenyin Fu ,  Kamal Sinha ,  Joydeep Ray

IPC: G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G09G5/36

CPC classification number: G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G09G5/363 ,  G09G5/366 ,  G09G2310/066 ,  G09G2310/08 ,  G09G2340/02 ,  G09G2360/06 ,  G09G2360/08 ,  G09G2370/022 ,  G09G2370/16

Abstract: In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.

公开(公告)号：US11995737B2

公开(公告)日：2024-05-28

申请号：US17527689

申请日：2021-11-16

Applicant: Intel Corporation

Inventor： Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  James A. Valerio ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06F9/5011 ,  Y02D10/00

Abstract: Thread dispatch circuitry is configured to dispatch threads of a two-dimensional (2D) thread group based on data access locality associated with the threads. The thread dispatch circuitry can dispatch a first 2D sub-group of the 2D thread group to a compute block of the multiple compute blocks, the first 2D sub-group associated with a first 2D tile of memory and dispatch a second 2D sub-group of the 2D thread group to the compute block of the multiple compute blocks, the second 2D sub-group associated with a second 2D tile of memory.

公开(公告)号：US20240134797A1

公开(公告)日：2024-04-25

申请号：US17973203

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： John A. Wiegert ,  Joydeep Ray ,  Vasanth Ranganathan ,  Biju George ,  Fangwen Fu ,  Abhishek R. Appu ,  Chunhui Mei ,  Changwon Rhee

IPC: G06F12/0855

CPC classification number: G06F12/0857 ,  G06F2212/1016

Abstract: Embodiments described herein provide a technique to facilitate the broadcast or multicast of asynchronous loads to shared local memory of a plurality of graphics cores within a graphics core cluster. One embodiment provides a graphics processor including a cache memory a graphics core cluster coupled with the cache memory. The graphics core cluster includes a plurality of graphics cores. The plurality of graphics cores includes a graphics core configured to receive a designation as a producer graphics core for a multicast load, read data from the cache memory; and transmit the data read from the cache memory to a consumer graphics core of the plurality of graphics cores.

公开(公告)号：US11961179B2

公开(公告)日：2024-04-16

申请号：US18305511

申请日：2023-04-24

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Subhajit Dasgupta ,  Srivallaba Mysore ,  Michael J. Norris ,  Vasanth Ranganathan ,  Joydeep Ray

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

Abstract: One embodiment provides for a graphics processing unit comprising a processing cluster to perform multi-rate shading via coarse pixel shading and output shaded coarse pixels for processing by a post-shader pixel processing pipeline.

公开(公告)号：US11954062B2

公开(公告)日：2024-04-09

申请号：US17310540

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： Joydeep Ray ,  Niranjan Cooray ,  Subramaniam Maiyuran ,  Altug Koker ,  Prasoonkumar Surti ,  Varghese George ,  Valentin Andrei ,  Abhishek Appu ,  Guadalupe Garcia ,  Pattabhiraman K ,  Sungye Kim ,  Sanjay Kumar ,  Pratik Marolia ,  Elmoustapha Ould-Ahmed-Vall ,  Vasanth Ranganathan ,  William Sadler ,  Lakshminarayanan Striramassarma

IPC: G06F12/00 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

公开(公告)号：US20240112295A1

公开(公告)日：2024-04-04

申请号：US17958216

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Biju George ,  Fangwen Fu ,  Supratim Pal ,  Jorge Parra ,  Chunhui Mei ,  Maxim Kazakov ,  Joydeep Ray

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06T1/20 ,  G06F9/30098 ,  G06F9/3836

Abstract: Shared local registers for thread team processing is described. An example of an apparatus includes one or more processors including a graphic processor having multiple processing resources; and memory for storage of data, the graphics processor to allocate a first thread team to a first processing resource, the first thread team including hardware threads to be executed solely by the first processing resource; allocate a shared local register (SLR) space that may be directly reference in the ISA instructions to the first processing resource, the SLR space being accessible to the threads of the thread team and being inaccessible to threads outside of the thread team; and allocate individual register spaces to the thread team, each of the individual register spaces being accessible to a respective thread of the thread team.