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    SHARED ACCELERATOR MEMORY SYSTEMS AND METHODS
    1.
    发明申请
    SHARED ACCELERATOR MEMORY SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20200310993A1

    公开(公告)日：2020-10-01

    申请号：US16370587

    申请日：2019-03-29

    Applicant: INTEL CORPORATION

    Inventor： Sanjay Kumar ,  David Koufaty ,  Philip Lantz ,  Pratik Marolia ,  Rajesh Sankaran ,  Koen Koning

    IPC: G06F13/16 ,  G06F12/1027 ,  G06F3/06

    Abstract: The present disclosure is directed to systems and methods sharing memory circuitry between processor memory circuitry and accelerator memory circuitry in each of a plurality of peer-to-peer connected accelerator units. Each of the accelerator units includes physical-to-virtual address translation circuitry and migration circuitry. The physical-to-virtual address translation circuitry in each accelerator unit includes pages for each of at least some of the plurality of accelerator units. The migration circuitry causes the transfer of data between the processor memory circuitry and the accelerator memory circuitry in each of the plurality of accelerator circuits. The migration circuitry migrates and evicts data to/from accelerator memory circuitry based on statistical information associated with accesses to at least one of: processor memory circuitry or accelerator memory circuitry in one or more peer accelerator circuits. Thus, the processor memory circuitry and accelerator memory circuitry may be dynamically allocated to advantageously minimize system latency attributable to data access operations.

    Coherency tracking apparatus and method for an attached coprocessor or accelerator
    2.
    发明授权
    Coherency tracking apparatus and method for an attached coprocessor or accelerator 有权

    公开(公告)号：US11379236B2

    公开(公告)日：2022-07-05

    申请号：US16728665

    申请日：2019-12-27

    Applicant: Intel Corporation

    Inventor： Pratik Marolia ,  Rajesh Sankaran

    IPC: G11C16/04 ,  G06F9/30 ,  G06F9/38 ,  G06F12/1027

    Abstract: An apparatus and method for hybrid software-hardware coherency. An apparatus comprises one or more processing elements to process data; a memory controller to couple the one or more processing elements to a device memory; an interconnect to couple the one or more processing elements to a host processor memory and to couple a host processor to the device memory; one or more device caches to store cache lines read from the host processor memory and/or the device memory; coherency circuitry to manage an ownership indication for each cache line, the ownership indication to be set to a first value to indicate ownership by the host processor and to be set to a second value to indicate ownership by the processing device, wherein the coherency circuitry is to transfer ownership of a first cache line from the processing device to the host processor by updating the ownership indication from the second value to the first value, the coherency circuitry to provide indirect access to the cache line by the processing device while the ownership indication is set to the first value, the coherency circuitry to maintain the ownership indication at the first value until receiving a request to change the ownership indication.

    Shared accelerator memory systems and methods
    5.
    发明授权
    Shared accelerator memory systems and methods 有权

    公开(公告)号：US10817441B2

    公开(公告)日：2020-10-27

    申请号：US16370587

    申请日：2019-03-29

    Applicant: INTEL CORPORATION

    Inventor： Sanjay Kumar ,  David Koufaty ,  Philip Lantz ,  Pratik Marolia ,  Rajesh Sankaran ,  Koen Koning

    IPC: G06F13/16 ,  G06F12/1027 ,  G06F3/06

    Abstract: The present disclosure is directed to systems and methods sharing memory circuitry between processor memory circuitry and accelerator memory circuitry in each of a plurality of peer-to-peer connected accelerator units. Each of the accelerator units includes virtual-to-physical address translation circuitry and migration circuitry. The virtual-to-physical address translation circuitry in each accelerator unit includes pages for each of at least some of the plurality of accelerator units. The migration circuitry causes the transfer of data between the processor memory circuitry and the accelerator memory circuitry in each of the plurality of accelerator circuits. The migration circuitry migrates and evicts data to/from accelerator memory circuitry based on statistical information associated with accesses to at least one of: processor memory circuitry or accelerator memory circuitry in one or more peer accelerator circuits. Thus, the processor memory circuitry and accelerator memory circuitry may be dynamically allocated to advantageously minimize system latency attributable to data access operations.

    PASID based routing extension for scalable IOV systems
    7.
    发明授权
    PASID based routing extension for scalable IOV systems 有权

    公开(公告)号：US12086082B2

    公开(公告)日：2024-09-10

    申请号：US17026516

    申请日：2020-09-21

    Applicant: Intel Corporation

    Inventor： Pratik Marolia ,  Sanjay Kumar ,  Rajesh Sankaran ,  Utkarsh Y. Kakaiya

    IPC: G06F13/20 ,  G06F3/06 ,  G06F9/455

    CPC classification number: G06F13/20 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0662 ,  G06F3/0679 ,  G06F9/45558

    Abstract: Methods and apparatus for PASID-based routing extension for Scalable IOV systems. The system may include a Central Processing Unit (CPU) operatively coupled to a scalable Input/Output Virtualization (IOV) device via an in-line device such as a smart controller or accelerator. A Control Process Address Space Identifier (C-PASID) associated with a first memory space is implemented in an Assignable Device Interface (ADI) for the IOV device. The ADI also implements a Data PASID (D-PASID) associated with a second memory space in which data are stored. The C-PASID is used to fetch a descriptor in the first memory space and the D-PASID is employed to fetch data in the second memory space. A hub embedded on the in-line device or implemented as a discrete device is used to steer memory access requests and/or fetches to the CPU or to the in-line device using the C-PASID and D-PASID. IOV devices include multi-PASID helper devices and off-the-shelf devices such as NICs with modified ADIs to support C-PASID and D-PASID usage.

    COHERENCY TRACKING APPARATUS AND METHOD FOR AN ATTACHED COPROCESSOR OR ACCELERATOR
    8.
    发明申请
    COHERENCY TRACKING APPARATUS AND METHOD FOR AN ATTACHED COPROCESSOR OR ACCELERATOR 有权

    公开(公告)号：US20210200545A1

    公开(公告)日：2021-07-01

    申请号：US16728665

    申请日：2019-12-27

    Applicant: Intel Corporation

    Inventor： Pratik Marolia ,  Rajesh Sankaran

    IPC: G06F9/30 ,  G06F9/38

    Abstract: An apparatus and method for hybrid software-hardware coherency. For example, one embodiment of an apparatus comprises: one or more processing elements to process data; a memory controller to couple the one or more processing elements to a device memory; an interconnect to couple the one or more processing elements to a host processor memory and to couple a host processor to the device memory; one or more device caches to store cache lines read from the host processor memory and/or the device memory; coherency circuitry to manage an ownership indication for each cache line, the ownership indication to be set to a first value to indicate ownership by the host processor and to be set to a second value to indicate ownership by the processing device, wherein the coherency circuitry is to transfer ownership of a first cache line from the processing device to the host processor by updating the ownership indication from the second value to the first value, the coherency circuitry to provide indirect access to the cache line by the processing device while the ownership indication is set to the first value, the coherency circuitry to maintain the ownership indication at the first value until receiving a request to change the ownership indication.

    Accelerator controller hub
    9.
    发明授权
    Accelerator controller hub 有权

    公开(公告)号：US12229069B2

    公开(公告)日：2025-02-18

    申请号：US17083200

    申请日：2020-10-28

    Applicant: Intel Corporation

    Inventor： Pratik Marolia ,  Andrew Herdrich ,  Rajesh Sankaran ,  Rahul Pal ,  David Puffer ,  Sayantan Sur ,  Ajaya Durg

    IPC: G06F13/40 ,  G06F13/42

    Abstract: Methods and apparatus for an accelerator controller hub (ACH). The ACH may be a stand-alone component or integrated on-die or on package in an accelerator such as a GPU. The ACH may include a host device link (HDL) interface, one or more Peripheral Component Interconnect Express (PCIe) interfaces, one or more high performance accelerator link (HPAL) interfaces, and a router, operatively coupled to each of the HDL interface, the one or more PCIe interfaces, and the one or more HPAL interfaces. The HDL interface is configured to be coupled to a host CPU via an HDL link and the one or more HPAL interfaces are configured to be coupled to one or more HPALs that are used to access high performance accelerator fabrics (HPAFs) such as NVlink fabrics and CCIX (Cache Coherent Interconnect for Accelerators) fabrics. Platforms including ACHs or accelerators with integrated ACHs support RDMA transfers using RDMA semantics to enable transfers between accelerator memory on initiators and targets without CPU involvement.

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