公开(公告)号：US20240292544A1

公开(公告)日：2024-08-29

申请号：US18528973

申请日：2023-12-05

Applicant: DAEDUCK ELECTRONICS CO., LTD.

Inventor： Seon-Kyu CHANG ,  Hee-Il RYU

IPC: H05K3/30 ,  H05K1/18 ,  H05K3/02

CPC classification number: H05K3/305 ,  H05K1/181 ,  H05K3/022 ,  H05K2201/10204

Abstract: The present invention discloses a fabrication method of thick-walled printed circuit board PCB), especially the packaging substrate for mounting thin wafer level components on the PCB substrate. The present invention provides a first embodiment of inserting a dummy at the circuit board manufacturing stage and a second embodiment of adjusting the thickness by inserting a dummy at the wafer processing stage.

公开(公告)号：US20240032208A1

公开(公告)日：2024-01-25

申请号：US18115871

申请日：2023-03-01

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Tae Hong MIN ,  Eun Su KWON

IPC: H05K3/46 ,  H05K1/03 ,  H05K3/40 ,  H05K3/12

CPC classification number: H05K3/4626 ,  H05K1/036 ,  H05K3/4007 ,  H05K3/1258 ,  H05K2203/049 ,  H05K2203/176 ,  H05K2201/10204

Abstract: A printed circuit board includes a first build-up insulating layer; an interconnect structure buried in an upper side of the first build-up insulating layer and including one or more insulating layers, one or more wiring layers, and one or more via layers; an adhesive disposed between an upper surface of the first build-up insulating layer and an upper surface of the interconnect structure, and having an upper surface exposed from the upper surface of the first build-up insulating layer; and a metal bump including a via portion penetrating the adhesive and a protrusion protruding to the upper surface of the adhesive.

公开(公告)号：US20190037686A1

公开(公告)日：2019-01-31

申请号：US15658717

申请日：2017-07-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James A. BUSBY ,  John R. DANGLER ,  Michael J. FISHER ,  David C. LONG

IPC: H05K1/02 ,  H05K1/09 ,  H05K1/11 ,  H05K1/18 ,  H05K5/02 ,  G01N27/04 ,  G06F21/87

CPC classification number: H05K1/0275 ,  G01N27/045 ,  G06F21/86 ,  G06F21/87 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/115 ,  H05K1/181 ,  H05K5/0208 ,  H05K2201/10151 ,  H05K2201/10204 ,  H05K2201/10371 ,  H05K2201/10522

Abstract: Tamper-respondent assemblies and methods of fabrication are provided which include at least one tamper-respondent sensor and a detector. The at least one tamper-respondent sensor includes conductive lines which form, at least in part, at least one tamper-detect network of the tamper-respondent sensor(s). In addition, the tamper-respondent sensor(s) includes at least one interconnect element associated with one or more conductive lines of the conductive lines forming, at least in part, the tamper-detect network(s). The interconnect element(s) includes at least one interconnect characteristic selected to facilitate obscuring a circuit lay of the at least one tamper-detect network. In operation, the detector monitors the tamper-detect network(s) of the tamper-respondent sensor(s) for a tamper event.

公开(公告)号：US20180042147A1

公开(公告)日：2018-02-08

申请号：US15488024

申请日：2017-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il-ju MUN ,  Keon KUK ,  Ji-woon YEOM

IPC: H05K9/00 ,  H05K1/18

CPC classification number: H05K1/182 ,  B05D1/26 ,  B05D7/50 ,  H01L23/552 ,  H01L2224/16227 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K9/0024 ,  H05K2201/09972 ,  H05K2201/10204 ,  H05K2203/0126

Abstract: An electromagnetic interference (EMI) shielding structure and a manufacturing method thereof are provided. The EMI shielding structure includes a shielding dam provided on a printed circuit board, the shielding dam forming a closed loop that defines a periphery of adjacent shielding regions of the printed circuit board; an insulating member that is provided on the adjacent shielding regions within the shielding dam, the insulating member covering circuit devices provided in the adjacent shielding regions; and a shielding member that covers an upper surface of the insulating member, wherein the shielding dam includes a border portion surrounding the adjacent shielding regions, and a partition portion disposed between the adjacent shielding regions and within the border portion.

公开(公告)号：US20180033719A1

公开(公告)日：2018-02-01

申请号：US15725144

申请日：2017-10-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/02 ,  H05K3/36 ,  H05K3/22 ,  H05K3/00 ,  H05K1/18 ,  H05K1/11 ,  H05K3/40 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: A semiconductor substrate includes: (1) a first dielectric structure having a first surface and a second surface opposite the first surface; (2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; (3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and (4) a second patterned conductive layer, disposed on and contacting the second surface of the first dielectric structure and including at least one conductive trace, wherein the first dielectric structure defines at least one opening, and a periphery of the opening corresponds to a periphery of the through hole of the second dielectric structure.

公开(公告)号：US20170373269A1

公开(公告)日：2017-12-28

申请号：US15609635

申请日：2017-05-31

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Taean SEO ,  Jinhwan CHOI ,  Junghun LEE

IPC: H01L51/52 ,  H01L51/00 ,  H05K1/11 ,  H05K1/02 ,  H01L27/32 ,  H05K1/18

CPC classification number: H01L51/5237 ,  G09F9/301 ,  H01L27/3223 ,  H01L27/3276 ,  H01L27/3293 ,  H01L51/0097 ,  H01L2251/5338 ,  H05K1/0201 ,  H05K1/111 ,  H05K1/181 ,  H05K7/20954 ,  H05K2201/10204

Abstract: A rollable display apparatus includes a flexible panel including a main panel with a display and a dummy panel with a wire connected to the display, a housing to accommodate the flexible panel, a rotatable rolling drum in the housing and coupled to a first end of the flexible panel, a supporting base moveable into and out of the housing and coupled to a second end of the flexible panel, and a printed circuit board connected to the second end of the flexible panel, the printed circuit board being on the supporting base.

公开(公告)号：US20170047295A1

公开(公告)日：2017-02-16

申请号：US15298234

申请日：2016-10-20

Applicant: Powertech Technology Inc.

Inventor： Yuan-Fu Lan ,  Hsien-Wen Hsu

IPC: H01L23/00 ,  H05K1/18 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H05K1/18 ,  H05K2201/10204

Abstract: A carrier substrate includes an insulation encapsulation, first conductive patterns, second conductive patterns, at least one first dummy pattern, and at least one second dummy pattern. The carrier substrate has a first layout region and a second layout region. The first conductive patterns and the first dummy pattern are located in the first layout region. The second conductive patterns and the second dummy pattern are located in the second layout region. The first and second conductive patterns and the first and second dummy patterns are embedded in the insulation encapsulation. The insulation encapsulation exposes top surfaces of the first and second conductive patterns and the first and second dummy patterns. The first dummy pattern and the second dummy pattern are insulated from the first conductive patterns and the second conductive patterns. An edge profile of the first dummy pattern facing the second dummy pattern is non-linear.

Abstract translation: 载体衬底包括绝缘封装，第一导电图案，第二导电图案，至少一个第一虚设图案和至少一个第二虚设图案。 载体基板具有第一布局区域和第二布局区域。 第一导电图案和第一虚设图案位于第一布局区域中。 第二导电图案和第二虚设图案位于第二布局区域中。 第一和第二导电图案以及第一和第二虚设图案嵌入在绝缘封装中。 绝缘封装暴露了第一和第二导电图案以及第一和第二虚拟图案的顶表面。 第一虚设图案和第二虚设图案与第一导电图案和第二导电图案绝缘。 面向第二虚拟图案的第一伪图案的边缘轮廓是非线性的。

公开(公告)号：US09485854B2

公开(公告)日：2016-11-01

申请号：US14464279

申请日：2014-08-20

Applicant: Intel Corporation

Inventor： Shaowu Huang ,  Kai Xiao ,  Beom-Taek Lee ,  Boping Wu ,  Xiaoning Ye

IPC: H05K1/02 ,  H01P3/08 ,  H01P11/00 ,  H05K1/09 ,  H05K3/30 ,  H05K1/18 ,  G06F1/16 ,  H01P1/26 ,  H01P5/16 ,  H04L25/03

CPC classification number: H05K1/023 ,  G06F1/16 ,  H01P1/268 ,  H01P3/08 ,  H01P5/16 ,  H01P11/003 ,  H01R12/737 ,  H01R13/6461 ,  H04L25/03006 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0246 ,  H05K1/0268 ,  H05K1/09 ,  H05K1/181 ,  H05K3/22 ,  H05K3/303 ,  H05K3/4007 ,  H05K2201/10159 ,  H05K2201/10204

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及布置在印刷电路板（PCB）组件中的互连件中的电信号吸收的技术和配置。 在一种情况下，PCB组件可以包括衬底和形成在衬底中以在PCB内布置电信号的互连。 互连可以与布置在PCB的表面上的连接部件耦合。 吸收材料可以设置在PCB上以与连接部件的至少一部分直接接触，以至少部分地吸收电信号的一部分。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160270219A1

公开(公告)日：2016-09-15

申请号：US15033836

申请日：2014-10-24

Applicant: INGENICO GROUP

Inventor： Stephane Pavageau ,  Xavier Lambert

IPC: H05K1/02 ,  H05K3/34 ,  H05K3/10 ,  B23K1/00

CPC classification number: H05K1/0284 ,  B23K1/0016 ,  B23K2101/42 ,  G06F21/86 ,  G06K7/0091 ,  H05K1/0275 ,  H05K3/10 ,  H05K3/1241 ,  H05K3/1275 ,  H05K3/143 ,  H05K3/245 ,  H05K3/34 ,  H05K2201/09409 ,  H05K2201/09781 ,  H05K2201/098 ,  H05K2201/10204 ,  H05K2203/0551

Abstract: A support is provided for fabrication of an electronic device. The support includes at least one component to be protected and at least one three-dimensional element of a height at least equal to a height of the electronic component. The three-dimensional element is disposed laterally opposite the at least one component to be protected. The three-dimensional element is chiefly constituted of a permanent assembling material.

Abstract translation: 提供了用于制造电子设备的支撑件。 支撑件包括至少一个待保护的部件和至少一个至少等于电子部件高度的高度的三维元件。 三维元件与要保护的至少一个部件横向相对设置。 三维元素主要由永久组装材料构成。

公开(公告)号：US20160057851A1

公开(公告)日：2016-02-25

申请号：US14464279

申请日：2014-08-20

Applicant: Intel Corporation

Inventor： Shaowu Huang ,  Kai Xiao ,  Beom-Taek Lee ,  Boping Wu ,  Xiaoning Ye

IPC: H05K1/02 ,  H01P3/08 ,  H01P11/00 ,  H05K1/09 ,  H05K3/30 ,  H05K1/18 ,  G06F1/16

CPC classification number: H05K1/023 ,  G06F1/16 ,  H01P1/268 ,  H01P3/08 ,  H01P5/16 ,  H01P11/003 ,  H01R12/737 ,  H01R13/6461 ,  H04L25/03006 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0246 ,  H05K1/0268 ,  H05K1/09 ,  H05K1/181 ,  H05K3/22 ,  H05K3/303 ,  H05K3/4007 ,  H05K2201/10159 ,  H05K2201/10204

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及布置在印刷电路板（PCB）组件中的互连件中的电信号吸收的技术和配置。 在一种情况下，PCB组件可以包括衬底和形成在衬底中以在PCB内布置电信号的互连。 互连可以与布置在PCB的表面上的连接部件耦合。 吸收材料可以设置在PCB上以与连接部件的至少一部分直接接触，以至少部分地吸收电信号的一部分。 可以描述和/或要求保护其他实施例。