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    CIRCUIT LAYOUTS OF TAMPER-RESPONDENT SENSORS
    2.
    发明申请
    CIRCUIT LAYOUTS OF TAMPER-RESPONDENT SENSORS 审中-公开

    公开(公告)号：US20170108543A1

    公开(公告)日：2017-04-20

    申请号：US14886179

    申请日：2015-10-19

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： William L. BRODSKY ,  James A. BUSBY ,  Edward N. COHEN ,  Phillip Duane ISAACS

    IPC: G01R31/02 ,  G01R3/00

    CPC classification number: H05K3/10 ,  G06F21/00 ,  G06F21/87 ,  H05K1/0275 ,  H05K1/028 ,  H05K2201/055 ,  H05K2201/09263

    Abstract: Tamper-respondent assemblies and methods of fabrication are provided which include a tamper-respondent electronic circuit structure. The tamper-respondent electronic circuit structure includes, for instance, a tamper-respondent sensor having at least one flexible layer and paired conductive lines disposed on the at least one flexible layer. The paired conductive lines form, at least in part, at least one tamper-detect network of the tamper-respondent sensor. The tamper-respondent electronic circuit structure further includes monitor circuitry electrically connected to the paired conductive lines to differentially monitor the paired conductive lines for a tamper event. In enhanced embodiments, multiple interconnect vias electrically connect to two or more layers of paired conductive lines and are disposed in an unfolded interconnect area of the tamper-respondent sensor when the sensor is operatively positioned about an electronic component or assembly to be protected.

    ENCLOSURE-TO-BOARD INTERFACE WITH TAMPER-DETECT CIRCUIT(S)
    4.
    发明申请
    ENCLOSURE-TO-BOARD INTERFACE WITH TAMPER-DETECT CIRCUIT(S) 审中-公开

    公开(公告)号：US20190261506A1

    公开(公告)日：2019-08-22

    申请号：US16285437

    申请日：2019-02-26

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Kathleen Ann FADDEN ,  James A. BUSBY ,  David C. LONG ,  John R. DANGLER ,  Alexandra ECHEGARAY ,  Michael J. FISHER ,  William SANTIAGO-FERNANDEZ

    IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11

    Abstract: Tamper-respondent assemblies and fabrication methods are provided which incorporate enclosure-to-circuit board protection. The tamper-respondent assemblies include a circuit board, and an enclosure mounted to the circuit board along an enclosure-to-board interface. The enclosure facilitates enclosing at least one electronic component coupled to the circuit board within a secure volume. A tamper-respondent electronic circuit structure facilitates defining the secure volume, and includes one or more tamper-detect circuits including at least one conductive trace disposed, at least in part, within the enclosure-to-board interface. The conductive trace(s) includes stress rise regions to facilitate tamper-detection at the enclosure-to-board interface. An adhesive is provided to secure the enclosure to the circuit board. The adhesive contacts, at least in part, the conductive trace(s) of the tamper-detect circuit(s) at the enclosure-to-board interface, including at the stress rise regions of the conductive trace(s).

    MULTI-LAYER STACK WITH EMBEDDED TAMPER-DETECT PROTECTION
    5.
    发明申请
    MULTI-LAYER STACK WITH EMBEDDED TAMPER-DETECT PROTECTION 审中-公开

    公开(公告)号：US20180365947A1

    公开(公告)日：2018-12-20

    申请号：US16048650

    申请日：2018-07-30

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： James A. BUSBY ,  Phillip Duane ISAACS ,  William SANTIAGO-FERNANDEZ

    IPC: G08B13/12

    CPC classification number: G08B13/12 ,  G08B13/128

    Abstract: Tamper-respondent assemblies and methods of fabrication are provided which include a multi-layer stack having multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers. Further, the tamper-respondent assembly includes a tamper-respondent electronic circuit structure embedded within the multi-layer stack. The tamper-respondent electronic circuit structure includes at least one tamper-respondent sensor embedded, at least in part, within at least one component layer of the multiple discrete component layers of the multi-layer stack. The tamper-respondent electronic circuit structure defines a secure volume within the multi-layer stack. For instance, the tamper-respondent electronic circuit structure may be fully embedded within the multi-layer stack, with monitor circuitry of the tamper-respondent electronic circuit structure residing within the secure volume within the multi-layer stack.

    TAMPER-RESPONDENT ASSEMBLY WITH INTERCONNECT CHARACTERISTIC(S) OBSCURING CIRCUIT LAYOUT
    9.
    发明申请
    TAMPER-RESPONDENT ASSEMBLY WITH INTERCONNECT CHARACTERISTIC(S) OBSCURING CIRCUIT LAYOUT 审中-公开

    公开(公告)号：US20200045812A1

    公开(公告)日：2020-02-06

    申请号：US16596941

    申请日：2019-10-09

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： James A. BUSBY ,  John R. DANGLER ,  Michael J. FISHER ,  David C. LONG

    IPC: H05K1/02 ,  G06F21/86 ,  H05K1/11 ,  H05K1/18 ,  H05K5/02 ,  G01N27/04 ,  G06F21/87

    Abstract: Tamper-respondent assemblies and methods of fabrication are provided which include at least one tamper-respondent sensor and a detector. The at least one tamper-respondent sensor includes conductive lines which form, at least in part, at least one tamper-detect network of the tamper-respondent sensor(s). In addition, the tamper-respondent sensor(s) includes at least one interconnect element associated with one or more conductive lines of the conductive lines forming, at least in part, the tamper-detect network(s). The interconnect element(s) includes at least one interconnect characteristic selected to facilitate obscuring a circuit lay of the at least one tamper-detect network. The at least one interconnect element is undetectable by x-ray, and the conductive lines are detectable by x-ray. In operation, the detector monitors the tamper-detect network(s) of the tamper-respondent sensor(s) for a tamper event.

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