公开(公告)号：US11251184B2

公开(公告)日：2022-02-15

申请号：US17039770

申请日：2020-09-30

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Yanbo Zhang ,  Huicai Zhong

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor arrangement includes: a substrate; fins formed on the substrate and extending in a first direction; gate stacks formed on the substrate and each extending in a second direction crossing the first direction to intersect at least one of the fins, and dummy gates composed of a dielectric and extending in the second direction; spacers formed on sidewalls of the gate stacks and the dummy gates; and dielectric disposed between first and second ones of the gate stacks in the second direction to electrically isolate the first and second gate stacks. The dielectric is disposed in a space surrounded by respective spacers of the first and second gate stacks which extend integrally. At least a portion of an interval between the first and second gate stacks in the second direction is less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.

公开(公告)号：US11215652B2

公开(公告)日：2022-01-04

申请号：US16065582

申请日：2015-12-25

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Guangwei Xu ,  Zhiheng Han ,  Wei Wang ,  Congyan Lu ,  Lingfei Wang ,  Ling Li ,  Ming Liu

IPC: G01R27/08 ,  G01R27/20

Abstract: A method for obtaining a contact resistance of a planar device includes: obtaining a contact resistance of a planar device by using a potential measurement method, in the measurement of the surface potential distribution, the planar device is in a state of current flowing, a certain voltage drop is formed at a junction area of the device; extracting the voltage drop measured through the Kelvin microscope by using a linear fitting method; and dividing the measured voltage drop by the current flowing through the device, thereby accurately calculating the magnitude of the contact resistance at the junction area of the planar device. With the present invention, the contact resistance of the planar device can be precisely measured, which is suitable for the contact resistance measurement experiments of devices such as thin film transistors and diodes. The invention has the advantages of reasonable theory, accurate result, simple and easy operation, and is favorable for optimizing the device performance and establishing a complete electrical model of the device.

公开(公告)号：US20210399018A1

公开(公告)日：2021-12-23

申请号：US17309222

申请日：2018-12-13

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu

IPC: H01L27/11597 ,  H01L21/28 ,  H01L27/11582

Abstract: A memory device and a method for manufacturing the same, and an electronic apparatus including the memory device are provided. The memory device may include: a substrate (1001); an electrode structure on the substrate (1001), in which the electrode structure includes a plurality of first electrode layers and a plurality of second electrode layers that are alternately stacked; a plurality of vertical active regions penetrating the electrode structure; a first gate dielectric layer and a second gate dielectric layer, in which the first gate dielectric layer is between the vertical active region and each first electrode layer of the electrode structure, and the second gate dielectric layer is between the vertical active region and each second electrode layer of the electrode structure, each of the first gate dielectric layer and the second gate dielectric layer constitutes a data memory structure. A first effective work function of a combination of the first electrode layer and the first gate dielectric layer is different from a second effective work function of a combination of the second electrode layer and the second gate dielectric layer.

公开(公告)号：US20210344115A1

公开(公告)日：2021-11-04

申请号：US16917503

申请日：2020-06-30

Applicant: ETHETA COMMUNICATION TECHNOLOGY (SHENZHEN) CO.,LTD ,  EAST CHINA RESEARCH INSTITUTE OF MICROELECTRONICS

Inventor： Huan-Chu HUANG ,  Jiaguo LU ,  Hong LIN ,  Junyong LIU ,  Zhixing QI ,  Minhui ZENG ,  Yanchao ZHOU ,  Jingwei LI ,  Tao MA

IPC: H01Q5/335 ,  H01Q5/50 ,  H01Q21/06 ,  H01Q9/04 ,  H01Q21/10

Abstract: The present invention relates to an integration module system of millimeter-wave and non-millimeter-wave antennas and an electronic apparatus, the system comprising a millimeter-wave antenna module and a non-millimeter-wave environment, the millimeter-wave antenna module forming a communication connection with the non-millimeter-wave environment for realizing reusing of the millimeter-wave antenna module to achieve a function of non-millimeter-wave antenna(s). The present invention proposes directly reusing a millimeter-wave antenna module, which is designed so that this module also has an antenna function of a non-millimeter-wave module, while an individual module's own volume does not need to be increased, and the module itself does not need to have additionally-added antenna traces, that is, with the same volume, a function of non-millimeter-wave antenna(s) may be further added. Therefore, it obviously helps to avoid an increase of the device's volume and improve compactness of the system and system design.

公开(公告)号：US20210335789A1

公开(公告)日：2021-10-28

申请号：US16626793

申请日：2018-09-21

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU

IPC: H01L27/108 ,  H01L29/423 ,  G11C11/4097 ,  G11C11/408

Abstract: A semiconductor memory device, a method of manufacturing the same, and an electronic device including the semiconductor memory device are disclosed. According to an embodiment, the semiconductor memory device may include a substrate; an array of memory cells provided on the substrate, wherein the memory cells are arranged in rows and columns, each of the memory cells comprises a pillar-shaped active region extending vertically, wherein the pillar-shaped active region comprises source/drain regions at upper and lower ends respectively and a channel region between the source/drain regions; and a plurality of bit lines formed on the substrate, wherein each of the bit lines is located below a corresponding one of the columns of memory cells and is electrically connected to the source/drain regions at lower ends of the respective memory cells in the corresponding column, wherein each of the memory cells further comprises a gate stack formed around a periphery of a corresponding channel region, and a respective one of the rows of memory cells has gate conductor layers included in the gate stacks of the respective memory cells in the row extending continuously in a direction of the row to form a corresponding one of word lines.

公开(公告)号：US11069808B2

公开(公告)日：2021-07-20

申请号：US16720231

申请日：2019-12-19

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang Yin ,  Qingzhu Zhang ,  Zhaohao Zhang ,  Tianchun Ye

IPC: H01L29/78 ,  H01L29/66

Abstract: A negative capacitance field effect transistor (NCFET) and a manufacturing method thereof. The NCFET includes: a substrate structure, including a MOS region; a gate insulating dielectric structure, covering the MOS region; and a metal gate stack layer, covering the gate insulating dielectric structure. The gate insulating dielectric structure includes an interface oxide layer, a HfO2 layer, a doping material layer, and a ferroelectric material layer, which are sequentially stacked along a direction away from the substrate structure. A ferroelectric material in the ferroelectric material layer is HfxA1-xO2, A represents a doping element, and 0.1≤x≤0.9. A material forming the doping material layer is AyOz or A, and a ratio of y/z is equal to 1/2, 2/3, 2/5 or 1/1. Ferroelectric characteristics, material stability, and material reliability of the NCFET are improved by increasing domain polarity of the ferroelectric material.

公开(公告)号：US20210193533A1

公开(公告)日：2021-06-24

申请号：US17250770

申请日：2018-10-31

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong ZHU ,  Yongkui ZHANG ,  Xiaogen YIN ,  Chen Li ,  Yongbo LIU ,  Kunpeng JIA

IPC: H01L21/8238 ,  H01L27/092

Abstract: The disclosed technology provides a semiconductor device, a manufacturing method thereof, and an electronic device including the device. An example semiconductor device includes a substrate; a first device and a second device on the substrate. Each of the first device and the second device include a first source/drain layer, a channel layer, and a second source layer that are sequentially stacked, from bottom to top, on the substrate, and a gate stack around at least a part of an outer periphery of the channel layer, with sidewalls of the respective channel layers of the first device and the second device extending at least partially along different crystal planes or crystal plane families.

公开(公告)号：US20210175333A1

公开(公告)日：2021-06-10

申请号：US17112690

申请日：2020-12-04

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L27/092

Abstract: A semiconductor device with a C-shaped active area and an electronic apparatus including the same is disclosed. The semiconductor device may include a first device and a second device opposite to each other on a substrate, each of which includes: a channel portion extending vertically on the substrate; source/drain portions located at the upper and lower ends of the channel portion and along the channel portion, the source/drain portions and the channel portion constitute a C-shaped structure; and a gate stack overlapping the channel portion on an inner sidewall of C-shaped structure, the gate stack has a portion surrounded by the C-shaped structure. The openings of the C-shaped structures of the two devices are opposite to each other. At least a portion of the gate stack of the first device close to the channel portion and that of the second device close to the channel portion are substantially coplanar.

公开(公告)号：US20210158753A1

公开(公告)日：2021-05-27

申请号：US17053992

申请日：2018-08-02

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Di GENG ,  Yue SU ,  Ling LI ,  Nianduan LU ,  Ming LIU

IPC: G09G3/3233 ,  G09G3/3291

Abstract: A pixel compensation circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and an organic light-emitting diode, each of the first transistor to the sixth transistor including a drain, a source and a gate.

公开(公告)号：US20210151613A1

公开(公告)日：2021-05-20

申请号：US17121396

申请日：2020-12-14

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Yan YANG ,  Zhihua Li ,  Wenwu Wang

IPC: H01L31/0232 ,  H01L31/02

Abstract: A method for integrating a surface-electrode ion trap and a silicon optoelectronic device, and an integrated structure. A silicon structure and a grating are formed on a wafer. A first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer are sequentially deposited above the wafer. An epitaxy opening is provided in the first dielectric layer to form single-photon avalanche detectors. First contacts vias connecting the detectors, and through silicon vias reaching a back surface of the wafer, are provided in the second dielectric layer and the third dielectric layer, respectively. Electrodes, the second contact vias and the third contact vias are provided in the fourth dielectric layer. The first contact vias are connected to a first electrode via the second contact vias, and the through silicon vias are connected to the first electrode and a second electrode via the third contact vias.