公开(公告)号：WO2011045083A1

公开(公告)日：2011-04-21

申请号：PCT/EP2010/006339

申请日：2010-10-18

Applicant: STMICROELECTRONICS S.R.L. ,  RICOTTI, Giulio ,  BOMPIERI, Paolo ,  ROSSI, Sandro

Inventor： RICOTTI, Giulio ,  BOMPIERI, Paolo ,  ROSSI, Sandro

IPC: H03K17/74

CPC classification number: H03K17/063

Abstract: The invention relates to a High Voltage switch configuration (10) having an input terminal (IN) which receives an input signal (Vin) to drive a load and an output terminal (OUT) which issues an output signal (Vout) to the load. Advantageously according to the invention, the High Voltage switch configuration ( 10) comprises at least a first and a second diode (D1, D2), being placed in antiseries between said input and output terminals (IN, OUT) and having a pair of corresponding terminals in common, in correspondence of a first internal circuit node (Xc1).

Abstract translation: 本发明涉及一种具有接收输入信号（Vin）以驱动负载的输入端（IN）和向负载发出输出信号（Vout）的输出端（OUT）的高压开关配置（10）。 有利地，根据本发明，高压开关配置（10）至少包括第一和第二二极管（D1，D2），放置在所述输入和输出端子（IN，OUT）之间的反电容中，并具有一对相应的 端子，对应于第一内部电路节点（Xc1）。

公开(公告)号：WO2010015388A1

公开(公告)日：2010-02-11

申请号：PCT/EP2009/005655

申请日：2009-08-05

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto

Inventor： PAGANI, Alberto

IPC: H01L23/58 ,  G01R31/28

CPC classification number: H01L22/32 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a circuit architecture for the parallel supplying of power during an electric or electromagnetic testing, such as EMWS or EWS or WLBI testing, of a plurality of electronic devices (2) each integrated on a same semiconductor wafer (1) wherein the electronic devices (1) are neatly provided on the semiconductor wafer (1) through integration techniques and have edges (5) bounded by separation scribe lines (7). Advantageously according to the invention, the circuit architecture comprises: - at least one conductive grid (4), interconnecting at least one group of the electronic devices (2) and having a portion being external (14) to the devices of the group and a portion being internal (13) to the devices of the group; the external portion (14) of the conductive grid (4) being extended also along the separation scribe lines (7); the internal portion (13) being extended within at least a part of the devices of the group; interconnection pads (6) between the external portion (14) and the internal portion (13) of the conductive grid (4) being provided on at least a part of the devices of the group, the interconnection pads (6) forming, along with the internal and external portions, power supply lines which are common to different electronic devices (2) of the group.

Abstract translation: 本发明涉及用于在电子或电磁测试（例如EMWS或EWS或WLBI测试）中并行供电的电路架构，每个电子设备（2）均集成在相同的半导体晶片（1）上，其中 电子器件（1）通过积分技术整齐地设置在半导体晶片（1）上并且具有由分隔划线（7）限定的边缘（5）。 有利地，根据本发明，电路架构包括： - 至少一个导电栅格（4），其将至少一组电子设备（2）互连并且具有到该组的设备的外部（14）的部分，以及 部分是内部（13）到组的装置; 导电栅格（4）的外部部分（14）也沿着分隔划线（7）延伸; 所述内部部分（13）在所述组的装置的至少一部分内延伸; 在外部部分（14）和导电栅格（4）的内部部分（13）之间的互连焊盘（6）设置在该组的至少一部分器件上，互连焊盘（6）连同 内部和外部部分，该组的不同电子设备（2）共同的电源线。

公开(公告)号：WO2008142712A1

公开(公告)日：2008-11-27

申请号：PCT/IT2007/000357

申请日：2007-05-21

Applicant: STMICROELECTRONICS S.R.L. ,  RUSSO, Riccardo ,  TORAZZINA, Aldo

Inventor： RUSSO, Riccardo ,  TORAZZINA, Aldo

IPC: H04L12/10

CPC classification number: H04L12/10 ,  G06F1/26

Abstract: In a reliable method and a relative circuit for monitoring the powering of a remote device through a LAN it is not necessary to generate an extra biasing voltage higher than the DC power supply voltage. As in known power distribution systems, the DC voltage used for supplying the remote device is applied to the LAN line and at the same time an AC voltage is applied to the same line for monitoring whether the remote device is connected or not to the LAN line. However, differently from prior techniques, the DC voltage is applied to a first or "high" terminal and the AC voltage is applied to the other or "low" terminal of the LAN line through a decoupling capacitor. This arrangement makes possible to supply the remote device with the largest possible DC voltage compatible with a fully integrated AC signal generator, disconnection detector and PSE controller and enhances the reliability of recognition of whether the powered device is connected to or disconnected from the LAN line.

Abstract translation: 在通过LAN监视远程设备的可靠方法和相关电路中，不需要产生高于直流电源电压的额外偏置电压。 如在已知的配电系统中，用于供应远程设备的直流电压被施加到LAN线路，同时将AC电压施加到同一线路上，用于监视远程设备是否连接到LAN线路 。 然而，与现有技术不同，DC电压被施加到第一或“高”端子，并且AC电压通过去耦电容器施加到LAN线路的另一个或“低”端。 这种布置使远程设备能够与完全集成的AC信号发生器，断开检测器和PSE控制器兼容的可能的最大直流电压提供给远程设备，并增强了识别被动设备是否连接到LAN线路或从LAN线路断开的可靠性。

公开(公告)号：WO2008026228A1

公开(公告)日：2008-03-06

申请号：PCT/IT2006/000629

申请日：2006-08-28

Applicant: STMICROELECTRONICS S.R.L. ,  ZAMPROGNO, Marco ,  CONFALONIERI, Pierangelo ,  MINUTI, Alberto

Inventor： ZAMPROGNO, Marco ,  CONFALONIERI, Pierangelo ,  MINUTI, Alberto

IPC: H03F3/00 ,  H03F3/45

CPC classification number: H03F3/005 ,  H03F3/45192 ,  H03F2203/45028 ,  H03F2203/45138 ,  H03F2203/45396 ,  H03F2203/45534 ,  H03F2203/45726

Abstract: An electrical circuit (1) for conversion from differential to single-ended is described, comprising: a differential amplifier stage (2) having a first (IN+) and a second (IN") input; a first (5) and a different second charging circuit (6) of the differential stage that can be operatively coupled, respectively, with an output (OUT*) of the conversion circuit (1) and with an auxiliary output (AUXOUT*). The circuit also comprises a first (7) and a second (8) buffer circuit each functionally arranged between one of said outputs\and between one of said charging circuits. The buffer circuits being configured so as to minimise a difference between the relative impedances seen towards said outputs (OUT*, AUXOUT*).

Abstract translation: 描述了用于从差分转换为单端的电路（1），包括：具有第一（IN +）和第二（IN“）输入的差分放大器级（2） 差动级的第一（5）和不同的第二充电电路（6），其可以分别与转换电路（1）的输出（OUT *）和辅助输出（AUXOUT *）可操作地耦合。 该电路还包括第一（7）和第二（8）缓冲电路，每个功能性地布置在所述输出端之一之间和所述充电电路之一之间。 缓冲器电路被配置为使得朝着所述输出（OUT *，AUXOUT *）看到的相对阻抗之间的差异最小化。

公开(公告)号：WO2008018094A1

公开(公告)日：2008-02-14

申请号：PCT/IT2006/000606

申请日：2006-08-07

Applicant: STMICROELECTRONICS S.R.L. ,  FAGNANI Mauro ,  BARTOLO Vincenzo ,  ADRAGNA Claudio

Inventor： FAGNANI Mauro ,  BARTOLO Vincenzo ,  ADRAGNA Claudio

IPC: G05F1/70 ,  H02M1/00

CPC classification number: G05F1/70

Abstract: Herein described is a control device of a device for the correction of the power factor in forced switching power supplies; said device for the correction of the power factor comprises a converter (20) and said control device (1) is coupled to the converter to obtain from an alternating input line voltage (Vin) a regulated output voltage (Vout) . The control device (1) comprises generating means (421-423) associated to a capacitor (Cf f) for generating a signal (Vff) representative of the root-mean- square value of the alternating line voltage; the generating means (421-424) are associated to means for discharging (Rf f) said capacitor. The control device comprises further means for discharging (Ml, COMPl, Cl; Ml 6, COMPI 1, CI 1; M50, COMP22, C0MP33, Cint) the capacitor (Cf f) suitable for discharging said capacitor when the signal (Vff) representative of the root-mean- square value of the alternating line voltage goes below a given value (VCl, VCI 1, Vint) .

Abstract translation: 这里描述了用于校正强制开关电源中的功率因数的装置的控制装置; 所述用于校正功率因数的装置包括转换器（20），并且所述控制装置（1）耦合到转换器以从交流输入线电压（Vin）获得调节输出电压（Vout）。 控制装置（1）包括与电容器（Cf f）相关联的产生装置（421-423），用于产生表示交流线路电压的均方根值的信号（Vff）; 发生装置（421-424）与用于放电（Rf f）所述电容器的装置相关联。 当信号（Vff）代表时，控制装置还包括用于放电（M1，COMP1，C1; M116，COMP1,1C1; M50，COMP22，C0MP33，Cint）适合于放电所述电容器的电容器（Cf f） 的交流线电压的均方根值低于给定值（VCl，VCI 1，Vint）。

公开(公告)号：WO2008012846A1

公开(公告)日：2008-01-31

申请号：PCT/IT2006/000576

申请日：2006-07-26

Applicant: STMICROELECTRONICS S.R.L. ,  MERASSI, Angelo ,  CORTESE, Mario, Francesco ,  VIOLA, Fultio ,  SIMONI, Barbara ,  RUSCONI CLERICI BELTRAMI, Andrea

Inventor： MERASSI, Angelo ,  CORTESE, Mario, Francesco ,  VIOLA, Fultio ,  SIMONI, Barbara ,  RUSCONI CLERICI BELTRAMI, Andrea

IPC: B81B7/00 ,  G01P15/08

CPC classification number: B81B3/0051 ,  B81B2201/0235 ,  B81B2201/0242 ,  G01P15/08 ,  G01P15/125 ,  G01P2015/0828

Abstract: Described herein is a microelectromechanical device (10) having a mobile mass (12) that undergoes a movement, in particular a spurious movement, in a first direction (z) in response to an external event; the device moreover has a stopper structure (14, 20) configured so as to stop said spurious movement. In particular, a stopper element (20) is fixedly coupled to the mobile mass (12) and is configured so as to abut against a stopper mass (14) in response to the spurious movement, thereby stopping it. In detail, the stopper element (20) is arranged on the opposite side of the stopper mass (14) with respect to a direction of the spurious movement, protrudes from the space occupied by the mobile mass (12) and extends in the space occupied by the stopper mass, in the first direction (z).

Abstract translation: 这里描述的是具有响应于外部事件在第一方向（z）上经历移动，特别是杂散运动的移动质量块（12）的微机电装置（10）。 该装置还具有构造成停止所述杂散运动的止动结构（14,20）。 特别地，止动元件（20）固定地联接到移动质量块（12），并且被配置为响应于伪运动而抵靠止动块（14），从而停止它。 详细地说，止动元件（20）相对于杂散运动的方向设置在止动块（14）的相对侧上，从可移动质量块（12）所占据的空间突出，并在占据的空间 通过止动块在第一方向（z）上。

公开(公告)号：WO2007122646A1

公开(公告)日：2007-11-01

申请号：PCT/IT2006/000273

申请日：2006-04-21

Applicant: STMICROELECTRONICS S.R.L. ,  GUARNERA, Alfio ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

Inventor： GUARNERA, Alfio ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/336 ,  H01L29/417 ,  H01L29/08 ,  H01L21/20 ,  H01L21/324 ,  H01L29/10 ,  H01L29/739 ,  H01L29/861 ,  H01L29/872

CPC classification number: H01L29/0634 ,  H01L21/2003 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872

Abstract: A process for manufacturing a power semiconductor device (25; 35) envisages the steps of: providing a body of semiconductor material (3) having a top surface (4) and having a first conductivity; forming columnar regions (6) having a second type of conductivity within the body of semiconductor material (3), and surface extensions (10) of the columnar regions (6) above the top surface (4); and forming doped regions (19, 20) having the second type of conductivity, in the proximity of the top surface (4) and in contact with the columnar regions (6). The doped regions (19, 20) are formed at least partially within the surface extensions (10) of the columnar regions (6); the surface extensions (10) and the doped regions (20) have a non-planar surface pattern, in particular with a substantially V-shaped groove.

Abstract translation: 一种用于制造功率半导体器件（25; 35）的工艺设想了以下步骤：提供具有顶表面（4）并具有第一导电性的半导体材料体（3）; 在所述半导体材料（3）的主体内形成具有第二导电类型的柱状区域（6）以及所述顶表面（4）上方的所述柱状区域（6）的表面延伸部（10）。 以及在所述顶表面（4）附近形成具有所述第二导电类型的掺杂区域（19,20）并与所述柱状区域（6）接触。 掺杂区域（19,20）至少部分地形成在柱状区域（6）的表面延伸部分（10）内; 表面延伸部（10）和掺杂区域（20）具有非平面的表面图案，特别是具有大致V形的凹槽。

公开(公告)号：WO2007091281A1

公开(公告)日：2007-08-16

申请号：PCT/IT2006/000062

申请日：2006-02-06

Applicant: STMICROELECTRONICS S.R.L. ,  POMPA, Pier, Paolo ,  FERRARA, Francesco ,  RINALDI, Ross

Inventor： POMPA, Pier, Paolo ,  FERRARA, Francesco ,  RINALDI, Ross

IPC: G01N21/00 ,  G01N33/00

CPC classification number: G01N21/7703 ,  B01L3/502715 ,  B01L7/525 ,  B01L2300/0654 ,  B01L2300/0819 ,  B01L2300/0877 ,  B01L2300/1827 ,  G01N21/6428 ,  G01N21/6452 ,  G01N21/6456 ,  G01N21/648 ,  G01N2021/7786

Abstract: A chip for nucleic acid analysis includes a body (2, 9) , in which a detection chamber (7) is formed for accommodating nucleic acid probes (12, 12') . A waveguide (8) is integrated in the body (2, 9) is and is arranged at the bottom of the detection chamber (7) so that an evanescent wave (EW) , produced at an interface (8a) of the waveguide (8) when a light radiation is conveyed within the waveguide (8), is irradiated towards the inside of the detection chamber (7) . An apparatus for inspection of nucleic acid probes includes: a holder (22) , on which a chip (1) for nucleic acid analysis is loaded, the chip containing nucleic acid probes (12, 12'); a light source (24) for supplying an excitation radiation to the nucleic acid probes (12, 12'); and an optical sensor (25) arranged so as to receive radiation coming from the nucleic acid probes (12, 12') .

Abstract translation: 用于核酸分析的芯片包括其中形成有用于容纳核酸探针（12,12'）的检测室（7）的主体（2,9）。 集成在体（2,9）中的波导（8）被布置在检测室（7）的底部，使得在波导（8）的界面（8a）处产生的ev逝波（EW） ）当在波导（8）内传送光辐射时朝向检测室（7）的内部照射。 用于检查核酸探针的装置包括：载体上用于核酸分析的芯片（1）的保持器（22），含芯片的核酸探针（12,12'）; 用于向核酸探针（12,12'）提供激发辐射的光源（24）; 以及布置成接收来自所述核酸探针（12,12'）的辐射的光学传感器（25）。

公开(公告)号：WO2007020016A1

公开(公告)日：2007-02-22

申请号：PCT/EP2006/007964

申请日：2006-08-11

Applicant: STMICROELECTRONICS S.R.L. ,  MICCICHE, Monica ,  GRIMALDI, Antonio, Giuseppe ,  ARCURI, Luigi

Inventor： MICCICHE, Monica ,  GRIMALDI, Antonio, Giuseppe ,  ARCURI, Luigi

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7811 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802

Abstract: Process for manufacturing a multi-drain power electronic device (30) characterised in that it comprises the following steps: forming a first semiconductor layer (21) of the first type of conductivity - forming at least a second semiconductor layer (23) of a second type of conductivity on the first semiconductor layer (21), forming, in this at least a second semiconductor layer (23), a first plurality of implanted regions (D3) of the first type of conductivity forming implanted body regions (40) of the second type of conductivity in portions of said second semiconductor layer (23) free from said first plurality of implanted regions (D3), - carrying out a thermal diffusion process so that the first plurality of implanted regions (D3) form a first plurality of electrically continuous implanted column regions (D) of the first type of conductivity along this at least a second semiconductor layer (23) and in electric contact with the first semiconductor layer (21).

Abstract translation: 一种用于制造多漏电功率电子器件（30）的方法，其特征在于，它包括以下步骤：形成第一类型导电的第一半导体层（21），形成第二半导体层的第二半导体层（23） 在第一半导体层（21）上形成导电性类型，在该至少第二半导体层（23）中形成第一导电形成植入体区域（40）的第一多个注入区域（D3） 在所述第二半导体层（23）的不含所述第一多个注入区域（D3）的部分中的第二类型的导电性， - 执行热扩散处理，使得所述第一多个注入区域（D3）形成第一多个电 沿着该至少第二半导体层（23）与第一半导体层（21）电接触的第一导电类型的连续注入的列区域（D）。

公开(公告)号：WO2007017515A3

公开(公告)日：2007-02-15

申请号：PCT/EP2006/065163

申请日：2006-08-08

Applicant: STMICROELECTRONICS S.R.L. ,  FONTANELLA, Luca ,  PASOLINI, Fabio ,  VIGNA, Benedetto ,  CHIESA, Enrico

Inventor： FONTANELLA, Luca ,  PASOLINI, Fabio ,  VIGNA, Benedetto ,  CHIESA, Enrico

IPC: G06F3/043

Abstract: In a device (2) for determining the position (P 1 (X, y) ) of a touch on a contact surface (Ia) , a plurality of vibration sensors (4) are configured to detect mechanical vibrations (9) generated by the touch on the contact surface (1a) and to generate corresponding vibration signals, and a processing circuit (6) is connected to the vibration sensors (4) and is configured to determine the touch position (P 1 (x, y) ) via a time-of-f light algorithm, based on differences between times of detection (t 1 , t 2 , t 3 ) of the mechanical vibrations (9) by the vibration sensors (4) .