公开(公告)号：EP4376388A1

公开(公告)日：2024-05-29

申请号：EP23306929.3

申请日：2023-11-09

Applicant: STMicroelectronics (ALPS) SAS ,  STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： RENNIG, Fred ,  TORRISI, Giovanni Luca ,  GAERTNER, Manuel ,  SIRITO-OLIVIER, Philippe ,  BURKHARDT, Fritz ,  OCCHIPINTI, Aldo

IPC: H04L67/12 ,  H04L12/40 ,  H04L12/12

CPC classification number: H04L2012/4021520130101 ,  H04L2012/4027320130101 ,  B60R16/023 ,  H04L12/12 ,  H04L12/40039

Abstract: In a vehicle communication network, a plurality of electronic control units (44'), ECUs, are arranged in groups. The ECUs pertaining to a same group are coupled to each other via a respective dedicated communication bus (59) operated according to a CAN protocol. A respective local controller (40') including a microcontroller unit (50) is coupled to each group of ECUs (44') via the respective dedicated communication bus (59) to exchange CAN frames therewith. A central controller is coupled to the local controllers (40') via a vehicle communication bus. Electrical loads (402-406) are coupled to the ECUs (44') to receive actuation signals therefrom and/or provide feedback signals thereto. Each microcontroller unit (50) of the local controllers (40') is configured as communication commander device to transmit and receive CAN frames via the respective dedicated communication bus (59). Each of the ECUs (44') includes a respective logic circuit (48') configured as communication responder device. In response to a CAN frame being received from the respective local controller (40'), the logic circuit (48') decodes the received CAN frame to produce the actuation signal for a respective electrical load (402-406). In response to a feedback signal being received from the respective electrical load (402-406), the logic circuit (48') transmits a CAN wake-up frame to the respective local controller (40') and encodes the feedback signal into a CAN frame for transmission to the respective local controller (40').

公开(公告)号：EP4254196A1

公开(公告)日：2023-10-04

申请号：EP23158845.0

申请日：2023-02-27

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V.

Inventor： COLOMBO, Roberto ,  SHARMA, Vivek Mohan ,  AGARWAL, Samiksha

IPC: G06F11/22 ,  G06F11/27 ,  G06F11/07

Abstract: A processing system (10a) comprising an address comparison circuit (40a) is described. The address comparison circuit (40a) is configured to compare an address value (IA) with an upper address limit (TAH) and a lower address limit (TAL). Specifically, for this purpose, a first iterative digital comparator (400) generates an upper-limit comparison signal (HH), a second iterative digital comparator (402) generates a lower-limit comparison signal (LH) and a combinational logic circuit (404) generates a combined comparison signal (RH).
In particular, a test circuit (42) sets the address value (IA), the upper address limit (TAH) and the lower address limit (TAL) to a given reference bit sequence and verifies whether the upper-limit comparison signal (HH) and/or the lower-limit comparison signal (LH) have the correct values. Moreover, the test circuit repeats various operations for each of the bits of the address value (IA). Specifically, the test circuit sets (5006) the respective bit of the address value (IA) to high and sets the respective bit of the upper address limit (TAH) and the lower address limit (TAL) to low. Next, the test circuit verifies (5006) whether the upper-limit comparison signal (HH) is de-asserted and/or whether the lower-limit comparison signal (LH) is asserted. Moreover, the test circuit sets (5010) the respective bit of the address value (IA) to low, and sets the respective bit of the upper address limit (TAH) and the lower address limit (TAL) to high. Next, the test circuit verifies (5012) whether the upper-limit comparison signal (HH) is asserted and/or whether the lower-limit comparison signal (LH) is de-asserted. Finally, the test circuit sets (5014) the respective bit of the address value (IA), the upper address limit (TAH) and the lower address limit (TAL) again to the same logic level (0_1).

公开(公告)号：EP4174659A1

公开(公告)日：2023-05-03

申请号：EP22201300.5

申请日：2022-10-13

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： GOYAL, Avneep Kumar ,  SZURMANT, Thomas ,  MARLETTI, Misaele ,  DAOLIO, Alessandro

IPC: G06F11/30 ,  G06F11/36 ,  G06F11/34

Abstract: A trace-data preparation circuit (300) including a filtering circuit (302) to receive traced memory-write data and a First In First Out buffer (306) coupled with the filtering circuit (302) to receive selected memory-write data filtered by the filtering circuit (302). The trace-data preparation circuit may further include a data compression circuit (308) to provide packaging data to a packaging circuit (310) that groups the selected memory-write data.

公开(公告)号：EP4138343A1

公开(公告)日：2023-02-22

申请号：EP22188198.0

申请日：2022-08-02

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

Inventor： RENNIG, Fred ,  DVORAK, Vaclav

IPC: H04L12/40

Abstract: A processing system (10a) is described. The processing system (10a) comprises a transmission terminal (TX) configured to provide a transmission signal (TXD), a reception terminal (RX) configured to receive a reception signal (RXD), a microprocessor (1020) programmable via software instructions, a memory controller (100) configured to be connected to a memory (104, 104b), a serial communication interface (50), and a communication system (114).
Specifically, the serial communication interface (50) supports a CAN FD Light mode of operation and a UART mode of operation. For this purpose, the serial communication interface (50) comprises a control register (CTRL), a clock management circuit (5044), a transmission shift register (5040; 5056), a transmission control circuit (5046), a reception shift register (5042; 5056) and a reception control circuit (5048).
Accordingly, the microprocessor (1020) may transmit and/or receive CAN FD Light or UART frames via the same serial communication interface (50).

公开(公告)号：EP4120083A1

公开(公告)日：2023-01-18

申请号：EP22181460.1

申请日：2022-06-28

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V.

Inventor： SHARMA, Vivek Mohan ,  COLOMBO, Roberto

IPC: G06F11/10 ,  G06F11/22 ,  G06F11/07

Abstract: A processing system (10a) is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit (SMb) comprising an error detection circuit (46) configured to receive data bits (DATA) and respective Error Correction Code, ECC, bits (ECC), wherein the data bits (DATA) correspond to the first, second or third data. The safety monitor circuit (SMb) calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit (120a) receives the error signal from the safety monitor circuits (SMb). In particular the safety monitor circuit (SMb) comprises a test circuit (480) configured to provide modified data bits and/or modified ECC bits to the error detection circuit (46) as a function of connectivity test control signals (CT), whereby the error detection circuit (46) asserts the error signal as a function of the connectivity test control signals (CT). The processing system (10a) comprises also a connectivity test control circuit (130) comprising control registers programmable via the microprocessor, wherein the connectivity test control signals (CT) are generated as a function of the content of the control registers.

公开(公告)号：EP4095704A1

公开(公告)日：2022-11-30

申请号：EP22174093.9

申请日：2022-05-18

Applicant: STMicroelectronics Application GmbH

Inventor： NANDLINGER, Rolf ,  COLOMBO, Roberto

IPC: G06F13/28

Abstract: A processing system (10a) is described. The processing system (10a) comprises a microprocessor (1020) programmable via software instructions, a memory controller (100) configured to be connected to a memory (104, 104b), a communication system (114) connecting the microprocessors (1020) to the memory controller (100), a cryptographic co-processor (40a) and a Serial Inter-Processor Interface, SIPI, communication interface (50a). The processign system (10a) also comprises a first (DMA T1 ) and a second configurable DMA channel (DMA T2 ).
Specifically, in a first configuration, the first DMA channel (DMA T1 ) is configured to transfer data from the memory (104b) to the cryptographic co-processor (40a), and the second DMA channel (DMA T2 ) is configured to transfer the encrypted data via two loops from the cryptographic co-processor (40a) to the SIPI communication interface (50a).
Conversely, in a second configuration, the second DMA channel (DMA T2 ) is configured to transfer received data via two loops from the SIPI communication interface (50a) to the cryptographic co-processor (40a), and the first DMA channel (DMA T1 ) is configured to transfer the decrypted data from the cryptographic co-processor (40a) to a memory (104b).

公开(公告)号：EP4075271A1

公开(公告)日：2022-10-19

申请号：EP22167299.1

申请日：2022-04-08

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V.

Inventor： COLOMBO, Roberto ,  SHARMA, Vivek Mohan

IPC: G06F9/455 ,  G06F11/07

Abstract: A processing system (10a) is described. The processing system comprises a plurality of safety monitoring circuits (SM) configured to generate a plurality of error signals (ERR) by monitoring the operation of a microprocessor, a memory controller and/or a resource.
In particular, the processing system comprises a plurality of fault collection subcircuits (32), wherein each fault collection sub-circuit (32) comprises one or more error combination circuits (320). Each error combination circuit (320) comprises a first programmable register (3204) and is configured to receive a subset of the error signals (ERR 1 , ..., ERR s ), determine whether one or more of the error signals (ERR 1 , ..., ERR s ) are asserted and store error status data to the first register (3204), which identifying the one or more asserted error signals (ERR 1 , ..., ERR s ). Moreover, each error combination circuit (320) is configured to read enable data from the first register and generate a combined error signal (CES) as a function of the error status data and the enable data.
The error management circuit (34) comprises a second programmable register and is configured to receive the combined error signals (CES), read routing data from the second register and generate for each microprocessor a respective signal (IRQ) used to signal an error as a function of the combined error signals (CES) and the routing data.

公开(公告)号：EP3547620B1

公开(公告)日：2020-11-25

申请号：EP19162919.5

申请日：2019-03-14

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

Inventor： RENNIG, Mr. Fred ,  BERAN, Mr. Ludek

IPC: H04L12/403 ,  G05B19/042 ,  G06F11/07 ,  H03M13/09

公开(公告)号：EP3404573A1

公开(公告)日：2018-11-21

申请号：EP18171177.1

申请日：2018-05-08

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： COLOMBO, Roberto ,  GROSSIER, Nicolas Bernard ,  DI SIRIO, Giovanni

IPC: G06F21/57 ,  G06F21/60 ,  H04L29/06 ,  G06F21/71 ,  H04L9/32 ,  G06F9/445

CPC classification number: G06F21/83 ,  G06F9/3816 ,  G06F9/445 ,  G06F12/02 ,  G06F21/57 ,  G06F21/64 ,  G06F21/74 ,  G06F2212/7209 ,  H04L9/3234 ,  H04L63/0853

Abstract: A hardware secure element is described. The hardware secure element comprises a processing unit and a receiver circuit configured to receive data comprising a command field (CMD) and a parameter field (P) adapted to contain a plurality of parameters.
The hardware secure element comprises also at least one hardware parameter check module (318) configured to receive at input a parameter to be processed (P(P_ID)) selected from said plurality of parameters, and process said parameter to be processed (P(P ID)) in order to verify whether said parameter (P(P_ID)) has given characteristics.
The hardware parameter check module (318) has associated one or more look-up tables (302c; 302d, 302e) configured to receive at input said command field (CMD) and a parameter index (P_ID) identifying said parameter to be processed (P(P_ID)) by said hardware parameter check module (318), and determine for said command field (CMD) and said parameter index (P_ID) a configuration data element (CDE), said configuration data element (CDE) comprising configuration information specifying the characteristics to be verified by said hardware parameter check module (318).

公开(公告)号：EP2652671B1

公开(公告)日：2015-04-22

申请号：EP11796992.3

申请日：2011-12-12

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics Application GmbH

Inventor： CHARLES, Alexandre ,  BÖHLER, Jürgen ,  MEZIACHE, Thierry ,  RIZZO, Pierre

IPC: G06K7/00 ,  G06K7/10 ,  H04W88/06

CPC classification number: H04W4/80 ,  G06K7/0008 ,  G06K7/10237 ,  G06K7/10247 ,  H04B5/0031

Abstract: A device, including a main element (ME) and a set of at least two auxiliary elements (SEi), said main element including a master SWP interface (MINT), each auxiliary element including a slave SWP interface (SLINTi) connected to said master SWP interface of said NFC element through a controllably switchable SWP link (LK) and management means (PRM, CTLM, AMGi) configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.

Abstract translation: 装置，包括一个主元素（ME），和一组至少两个辅助元件（SEI）的，所述包括主SWP接口（MINT），每个辅助元件，其包括连接到所述主SWP从属SWP接口（SLINTi）主元件 通过所述可控开关的SWP链路（LK）和配置成控制所述SWP链路切换用于选择性地激活在一次在所述SWP链路只有一个从SWP接口管理装置（PRM，CTLM，AMGI）NFC元件的接口。