公开(公告)号：US20150334850A1

公开(公告)日：2015-11-19

申请号：US14707295

申请日：2015-05-08

Applicant: NGK SPARK PLUG CO., LTD.

Inventor： Takahiro HAYASHI

IPC: H05K3/46 ,  H05K1/02

CPC classification number: H05K3/28 ,  H05K1/0284 ,  H05K3/188 ,  H05K3/243 ,  H05K3/244 ,  H05K3/282 ,  H05K3/381 ,  H05K3/383 ,  H05K3/4007 ,  H05K3/46 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/09409 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/10204 ,  H05K2203/0307 ,  H05K2203/0574 ,  H05K2203/058 ,  H05K2203/0597 ,  H05K2203/0766 ,  Y10T29/49156

Abstract: A method of manufacturing a wiring substrate according to the present invention includes a step of forming a wiring layer including connection terminals on a first insulating layer; a step of forming a second insulating layer on the wiring layer and on the first insulating layer; a step of forming electrically insulative dummy portions separated from the wiring layer on the first insulating layer through patterning of the second insulating layer; a step of forming a third insulating layer on the wiring layer, on the dummy portions, and on the first insulating layer; and a step of forming openings in the third insulating layer for exposing the connection terminals in such a manner that upper end portions of the connection terminals protrude from the third insulating layer, and lower end portions of the connection terminals are embedded in the third insulating layer.

Abstract translation: 根据本发明的制造布线基板的方法包括在第一绝缘层上形成包括连接端子的布线层的步骤; 在所述布线层和所述第一绝缘层上形成第二绝缘层的步骤; 通过图案化所述第二绝缘层而形成与所述第一绝缘层上的所述布线层分离的电绝缘的虚设部分的步骤; 在所述布线层上，所述虚拟部分上和所述第一绝缘层上形成第三绝缘层的步骤; 以及在所述第三绝缘层中形成用于暴露所述连接端子的开口的步骤，使得所述连接端子的上端部从所述第三绝缘层突出，并且所述连接端子的下端部嵌入所述第三绝缘层 。

公开(公告)号：US20150242025A1

公开(公告)日：2015-08-27

申请号：US14191484

申请日：2014-02-27

Applicant: Ronald Steven Cok

Inventor： Ronald Steven Cok

IPC: G06F3/047 ,  G06F3/044

CPC classification number: G06F3/044 ,  G06F1/16 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/042 ,  G06F3/046 ,  G06F3/047 ,  G06F2203/04103 ,  G06F2203/04107 ,  G06F2203/04111 ,  G06F2203/04112 ,  H05K1/0216 ,  H05K1/0296 ,  H05K2201/10204 ,  Y10T29/49105 ,  Y10T29/49117

Abstract: A method of making a micro-wire electrode structure includes providing a substrate having a surface. A plurality of first micro-wire electrodes spatially separated by first electrode gaps is located in a first layer in relation to the surface, each first micro-wire electrode including a plurality of electrically connected first micro-wires. A plurality of electrically isolated second micro-wire electrodes in a second layer is located in relation to the surface, the second layer at least partially different from the first layer and each second micro-wire electrode including a plurality of electrically connected second micro-wires. A plurality of first gap micro-wires is located in each first electrode gap, at least some of the first gap micro-wires located in a gap layer different from the first layer, the first gap micro-wires electrically isolated from the first micro-wires.

Abstract translation: 制造微线电极结构的方法包括提供具有表面的衬底。 通过第一电极间隙空间分隔的多个第一微线电极位于相对于表面的第一层中，每个第一微线电极包括多个电连接的第一微线。 第二层中的多个电隔离的第二微线电极相对于表面定位，第二层至少部分地不同于第一层，每个第二微线电极包括多个电连接的第二微线 。 多个第一间隙微细线位于每个第一电极间隙中，至少一些第一间隙微线位于不同于第一层的间隙层中，第一间隙微线与第一微缝隙电绝缘， 电线

公开(公告)号：US20150242010A1

公开(公告)日：2015-08-27

申请号：US14191482

申请日：2014-02-27

Applicant: RONALD STEVEN COK

Inventor： RONALD STEVEN COK

IPC: G06F3/044 ,  H05K1/02

CPC classification number: G06F3/044 ,  G06F1/16 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/042 ,  G06F3/046 ,  G06F3/047 ,  G06F2203/04103 ,  G06F2203/04107 ,  G06F2203/04111 ,  G06F2203/04112 ,  H05K1/0216 ,  H05K1/0296 ,  H05K2201/10204 ,  Y10T29/49105 ,  Y10T29/49117

Abstract: A micro-wire electrode structure includes a substrate having a surface. A plurality of first micro-wire electrodes spatially separated by first electrode gaps is located in a first layer in relation to the surface, each first micro-wire electrode including a plurality of electrically connected first micro-wires. A plurality of electrically isolated second micro-wire electrodes is located in a second layer in relation to the surface, the second layer at least partially different from the first layer. Each second micro-wire electrode includes a plurality of electrically connected second micro-wires. A plurality of first gap micro-wires is located in each first electrode gap, at least some of the first gap micro-wires located in a gap layer different from the first layer. The first gap micro-wires are electrically isolated from the first micro-wires.

Abstract translation: 微线电极结构包括具有表面的基板。 通过第一电极间隙空间分隔的多个第一微线电极位于相对于表面的第一层中，每个第一微线电极包括多个电连接的第一微线。 多个电隔离的第二微线电极相对于表面位于第二层中，第二层至少部分地不同于第一层。 每个第二微线电极包括多个电连接的第二微线。 多个第一间隙微细线位于每个第一电极间隙中，至少一些第一间隙微细线位于不同于第一层的间隙层中。 第一间隙微线与第一微线电隔离。

公开(公告)号：US20150230332A1

公开(公告)日：2015-08-13

申请号：US14424831

申请日：2013-08-06

Applicant: Robert Bosch GmbH

Inventor： Tobias Stiefel

IPC: H05K1/02

CPC classification number: H05K1/0259 ,  H02K11/26 ,  H05K2201/10204

Abstract: Surge arrester for a an electric machine, comprising a dummy component (2) which is, compared to components on a circuit board (1) of the electric machine, mounted at the shortest distance from a discharge element (4) of the electric machine, the dummy component (2) being connected to earth potential in at least one terminal.

Abstract translation: 与电机的电路板（1）上的与电动机的排出元件（4）最短距离安装的部件相比，包括一个虚拟部件（2）的电动避雷器， 所述虚拟部件（2）在至少一个端子中连接到地电位。

公开(公告)号：US20150076113A1

公开(公告)日：2015-03-19

申请号：US14481572

申请日：2014-09-09

Applicant: ASAHI GLASS COMPANY, LIMITED

Inventor： Kohei HORIUCHI

IPC: B44C1/22

CPC classification number: B44C1/228 ,  B23K26/382 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/50 ,  B23K2103/54 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/0029 ,  H05K2201/09836 ,  H05K2201/10204 ,  H05K2203/163 ,  H01L2924/00

Abstract: A method including a) forming a through-hole in a dummy substrate including a surface by radiating a laser to the surface of the dummy substrate in a state where the dummy substrate is moved relative to the laser along a direction parallel to the surface of the dummy substrate, b) determining an angle α (−90°

Abstract translation: 一种方法，包括：在虚拟衬底相对于激光器沿着平行于所述虚拟衬底的表面的方向相对于激光器移动的状态下，通过在所述虚设衬底的表面辐射激光而在包括表面的虚设衬底中形成通孔 虚拟基板，b）确定通孔相对于垂直于虚设基板的表面的线的角度α（-90°<α<+ 90°），以及c）在绝缘基板中形成通孔 与步骤a）相同的条件，除了以角度＆bgr辐射激光; 相对于垂直于绝缘基板的表面的线。 角度＆bgr 被设定为相对于垂直于绝缘基板的表面的线的角度α线对称，并且满足＆bgr =α的关系。

公开(公告)号：US20150062850A1

公开(公告)日：2015-03-05

申请号：US14104632

申请日：2013-12-12

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Cheol Ho CHOI ,  Sung Jin Chun ,  Seok Kyu Lee ,  Dong Hoon Kim

IPC: H05K1/02

CPC classification number: H05K1/0271 ,  H05K1/185 ,  H05K3/4697 ,  H05K2201/10204

Abstract: Disclosed herein is a printed circuit board of a build-up structure in which an insulating layer and a circuit layer are stacked on a core layer, the core layer including: an electronic chip cavity in which an electronic chip is accommodated; and a dummy chip cavity in which a dummy chip is accommodated to offset warpage by the electronic chip.

Abstract translation: 本发明公开了一种堆积结构的印刷电路板，其中绝缘层和电路层堆叠在芯层上，芯层包括：容纳电子芯片的电子芯片腔; 以及虚拟芯片空腔，其中容纳虚拟芯片以抵消电子芯片的翘曲。

公开(公告)号：US20150010694A1

公开(公告)日：2015-01-08

申请号：US14316382

申请日：2014-06-26

Applicant: TAIYO YUDEN CO., LTD.

Inventor： Masashi MIYAZAKI ,  Yuichi SUGIYAMA ,  Tatsuro SAWATARI ,  Hideki YOKOTA ,  Yutaka HATA

IPC: H05K3/06 ,  H05K3/44

CPC classification number: H05K3/4697 ,  B05D3/12 ,  B05D5/12 ,  H05K1/185 ,  H05K3/0044 ,  H05K3/007 ,  H05K3/0094 ,  H05K3/04 ,  H05K3/06 ,  H05K3/30 ,  H05K3/42 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4647 ,  H05K2201/10204

Abstract: The method of manufacturing a substrate includes: forming a penetrating hole in a base layer; inserting a metal dummy part in the penetrating hole; forming an insulating portion made of synthetic resin to fill a ring-shaped gap between the penetrating hole and the dummy part; forming lower insulating layers, covering the bottom surface of the dummy part, that are made of synthetic resin on the bottom surface of the base layer to be continuous with the insulating portion; forming upper insulating layers, covering the top surface of the dummy part, that are made of synthetic resin on the top surface of the base layer to be continuous with the insulating portion; forming an exposing hole by routing in the upper insulating layers to expose the top surface of the dummy part; and forming a cavity by removing the dummy part exposed through the exposing hole by etching.

Abstract translation: 制造基板的方法包括：在基层中形成贯通孔; 将金属虚设部件插入穿透孔中; 形成由合成树脂制成的绝缘部分，以填充所述穿透孔和所述虚拟部件之间的环形间隙; 在所述基底层的底面上形成覆盖所述虚拟部的底面的由合成树脂制成的下绝缘层，以与所述绝缘部连续; 在所述基底层的顶表面上形成覆盖所述虚拟部分的上表面的由合成树脂制成的上绝缘层，以与所述绝缘部分连续; 通过在上绝缘层中布线来形成暴露孔以暴露虚拟部分的顶表面; 并且通过蚀刻去除暴露在暴露孔中的虚拟部分来形成空腔。

公开(公告)号：US20140215805A1

公开(公告)日：2014-08-07

申请号：US13757811

申请日：2013-02-03

Applicant: QUALCOMM INCORPORATED

Inventor： Yang ZHANG ,  Jack B. STEENSTRA

IPC: H05K13/00

CPC classification number: H05K13/00 ,  H05K1/0218 ,  H05K3/284 ,  H05K3/288 ,  H05K2201/10204 ,  H05K2201/10371 ,  H05K2203/0173 ,  Y10T29/49004

Abstract: A method for manufacturing a removable metalized conformal shield for a circuit substrate having at least one circuit component includes: forming a cast representing the circuit substrate having the at least one circuit component; preparing a metalized conformal shield using the cast; applying the metalized conformal shield to the circuit substrate; measuring an output of the circuit component of the circuit substrate; removing the metalized conformal shield from the circuit substrate; and adjusting the circuit component based on the measured output.

Abstract translation: 一种用于制造具有至少一个电路部件的电路基板的可拆卸金属化共形屏蔽的方法，包括：形成表示具有所述至少一个电路部件的电路基板的铸件; 使用铸件制备金属化保形盾; 将金属化的共形屏蔽施加到电路基板; 测量电路基板的电路部件的输出; 从电路基板去除金属化的共形屏蔽; 并且基于测量的输出来调整电路部件。

公开(公告)号：US08730677B2

公开(公告)日：2014-05-20

申请号：US13324770

申请日：2011-12-13

Applicant: Toni Wald ,  Sven Liborius

Inventor： Toni Wald ,  Sven Liborius

IPC: H05K7/20

CPC classification number: H05K1/0209 ,  H05K1/0207 ,  H05K3/341 ,  H05K2201/066 ,  H05K2201/10204

Abstract: The invention relates to a method of cooling electronic circuit boards using surface mounted devices (SMD), the method comprising the steps of: after or during the board layout, filling empty spaces V1, V2, V3, V4, V5, V6, V7, V8, V9, V10 with at a number of heat sink devices 1, 2, 3, 4, 5 near a thermal hot spot and connecting the number of heat sink devices 1, 2, 3, 4, 5 to a thermally conducting path 25, 27, 29, 31, 33, 35 of the board N, respectively. Further, the invention relates to a heat sink device 1, 2, 3, 4, 5 adapted to implement the method according to the invention.

Abstract translation: 本发明涉及使用表面贴装装置（SMD）冷却电子电路板的方法，该方法包括以下步骤：在电路板布局之后或期间填充空的空间V1，V2，V3，V4，V5，V6，V7， V8，V9，V10，其中多个散热装置1,2,3,4,5在热热点附近并将多个散热装置1,2,3,4,5连接到导热路径25 ，N号分别为27,29,31,33,35。 此外，本发明涉及适于实现根据本发明的方法的散热设备1,2,3,4,5。

公开(公告)号：US08508235B2

公开(公告)日：2013-08-13

申请号：US12958982

申请日：2010-12-02

Applicant: Swen Weitemeier ,  Christian Oldendorf

Inventor： Swen Weitemeier ,  Christian Oldendorf

IPC: H01H31/02

CPC classification number: G01R31/2815 ,  G01R31/2839 ,  G06F21/86 ,  H05K1/0275 ,  H05K2201/10151 ,  H05K2201/10204

Abstract: An electronic device, and associated method, provided with a circuit board (10), with a set of input contacts (IN/COM), a set of output contacts (OUT/COM) and an electrical circuit (18) connected between the input contacts (IN/COM) and the output contacts (OUT/COM) and a controller. The controller carries out a real-time test of the circuit board using a test signal introduced into the electrical circuit, the electrical circuit (18) being designed as a passive network having a characteristic transfer function and provided with at least one capacitive element, wherein the capacitive element is a conductor surface (221) forming a capacitor in the assembled state with a corresponding, device-side conductor surface (222″), which is connected to the electrical circuit (18) via a contact element in the assembled state, whereby the capacitive value of the capacitive element in the assembled state differs from the capacitive value of the capacitive element in the disassembled state.

Abstract translation: 一种具有电路板（10）的电子设备和相关方法，具有一组输入触点（IN / COM），一组输出触点（OUT / COM）和连接在输入端之间的电路（18） 触点（IN / COM）和输出触点（OUT / COM）和控制器。 控制器使用引入电路的测试信号对电路板进行实时测试，电路（18）被设计为具有特征传递函数并具有至少一个电容元件的无源网络，其中 电容性元件是在组装状态下形成电容器的导体表面（221），其中相应的器件侧导体表面（222“）经由组装状态的接触元件连接到电路（18） 由此，组装状态下的电容元件的电容值与分解状态下的电容元件的电容值不同。