公开(公告)号：WO2007078958A2

公开(公告)日：2007-07-12

申请号：PCT/US2006048555

申请日：2006-12-18

Applicant: INTEL CORP ,  MADUKKARUMUKUMANA RAJESH SANKA ,  MUTHRASANALLUR SRIDHAR ,  HUGGAHALLI RAMAKRISHNA ,  ILLIKKAL RAMESHKUMAR

Inventor： MADUKKARUMUKUMANA RAJESH SANKA ,  MUTHRASANALLUR SRIDHAR ,  HUGGAHALLI RAMAKRISHNA ,  ILLIKKAL RAMESHKUMAR

IPC: G06F12/10 ,  G06F12/08 ,  G06F12/14

CPC classification number: G06F12/0879 ,  G06F12/0862 ,  G06F12/1036 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/145 ,  G06F13/28

Abstract: Embodiments of an apparatus, method, and system for encoding direct cache access transactions based on a memory access data structure are disclosed. In one embodiment, an apparatus includes memory access logic and transaction logic. The memory access logic is to determine whether to allow a memory access based on a memory access data structure. The transaction logic is to assign direct cache access attributes to a transaction based on the memory access data structure.

Abstract translation: 公开了一种用于基于存储器访问数据结构对直接高速缓存访​​问事务进行编码的装置，方法和系统的实施例。 在一个实施例中，装置包括存储器访问逻辑和事务逻辑。 存储器访问逻辑是确定是否允许基于存储器访问数据结构的存储器访问。 事务逻辑是基于存储器访问数据结构将直接高速缓存访​​问属性分配给事务。

公开(公告)号：WO2004099992A3

公开(公告)日：2005-06-02

申请号：PCT/US2004013485

申请日：2004-04-30

Applicant: SILICON GRAPHICS INC ,  UNIV UTAH

Inventor： MILLER STEVEN C ,  DENEROFF MARTIN M ,  SCHIMMEL CURT F ,  CARTER JOHN ,  ZHANG LIXIN ,  PARKER MICHAEL

IPC: G06F12/10 ,  G06F12/00

CPC classification number: G06F12/1036 ,  G06F12/1027

Abstract: An address translation unit generates a physical address for access to a memory from a virtual address using either a translation lookaside buffer or a segmentation buffer. If the virtual address falls within a predetermined range, the address translation unit will use the segmentation buffer to generate the physical address. Upon generation of the physical address, the memory will either receive data from or provide data to a processor in accordance with the instructions being processed by the processor.

Abstract translation: 地址转换单元使用翻译后备缓冲器或分段缓冲器从虚拟地址生成用于访问存储器的物理地址。 如果虚拟地址落在预定范围内，则地址转换单元将使用分段缓冲器来生成物理地址。 在生成物理地址时，存储器将根据由处理器处理的指令从数据接收数据或向处理器提供数据。

公开(公告)号：WO2004099992A2

公开(公告)日：2004-11-18

申请号：PCT/US2004/013485

申请日：2004-04-30

Applicant: SILICON GRAPHICS, INC. ,  THE UNIVERSITY OF UTAH

Inventor： MILLER, Steven, C. ,  DENEROFF, Martin, M. ,  SCHIMMEL, Curt, F. ,  CARTER, John ,  ZHANG, Lixin ,  PARKER, Michael

IPC: G06F12/00

CPC classification number: G06F12/1036 ,  G06F12/1027

Abstract: An address translation unit generates a physical address for access to a memory from a virtual address using either a translation lookaside buffer or a segmentation buffer. If the virtual address falls within a predetermined range, the address translation unit will use the segmentation buffer to generate the physical address. Upon generation of the physical address, the memory will either receive data from or provide data to a processor in accordance with the instructions being processed by the processor.

Abstract translation: 地址转换单元使用翻译后备缓冲器或分段缓冲器从虚拟地址生成用于访问存储器的物理地址。 如果虚拟地址落在预定范围内，则地址转换单元将使用分段缓冲器来生成物理地址。 在生成物理地址时，存储器将根据由处理器处理的指令从数据接收数据或向处理器提供数据。

公开(公告)号：WO9821712A3

公开(公告)日：1998-07-09

申请号：PCT/US9720610

申请日：1997-11-12

Applicant: IDEA CORP

Inventor： YAMADA KOICHI ,  HAMMOND GARY NEIL

IPC: G06F12/10 ,  G11B

CPC classification number: G06F12/1036 ,  G06F2212/681

Abstract: A method and an apparatus for translating a virtual address (305) into a physical address (315) in a multiple region virtual memory environment. In one embodiment, a translation lookside buffer (TLB) (313) is configured to provide page table entries to build a physical address. The TLB is supplemented with a virtual hash page table (VHPT) (325) to provide TLB entries in the occurrences of TLB misses. An alternate software replacement scheme may be utilized on a per region basis instead of the default page table walk of the VHPT with a dedicated bit (311) associated with each particular region of the disclosed virtual address space. A VHPT walk is performed only if the particular bit for the particular region and a master enable bit (319) are both enabled. Otherwise, the alternate software replacement routine is performed to provide TLB replacements in the occurrences of TLB misses.

公开(公告)号：WO1997034229A1

公开(公告)日：1997-09-18

申请号：PCT/US1997003593

申请日：1997-03-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  NOVAK, Stephen, T. ,  HONG-YI, Chen

IPC: G06F12/10

CPC classification number: G06F12/0848 ,  G06F12/1036

Abstract: A Microprocessor having a segment descriptor cache (24) that holds data obtained from a segment descriptor table (26) contained in an external memory (14) and a separate data cache (22) that holds data obtained from portions of the external memory (14) other than the segment descriptor table (26).

Abstract translation: 一种具有段描述符高速缓存（24）的微处理器，其保存从包含在外部存储器（14）中的段描述符表（26）获得的数据和保存从外部存储器（14）的部分获得的数据的单独数据高速缓存（22） ），而不是段描述符表（26）。

公开(公告)号：WO2018208526A1

公开(公告)日：2018-11-15

申请号：PCT/US2018/030184

申请日：2018-04-30

Applicant: QUALCOMM INCORPORATED

Inventor： SENIOR, Richard ,  KOOB, Christopher, Edward ,  CHHABRA, Gurvinder, Singh ,  OPORTUS VALENZUELA, Andres, Alejandro ,  GENG, Nieyan ,  RAGHAVENDRA, Raghuveer ,  PORTER, Christopher ,  JANAKIRAMAN, Anand

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/02

CPC classification number: G06F12/1036 ,  G06F3/0685 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/60

Abstract: Reducing metadata size in compressed memory systems of processor-based systems is disclosed. In one aspect, a compressed memory system provides 2 N compressed data regions, corresponding 2 N sets of free memory lists, and a metadata circuit. The metadata circuit associates virtual addresses with abbreviated physical addresses, which omit N upper bits of corresponding full physical addresses, of memory blocks of the 2 N compressed data regions. A compression circuit of the compressed memory system receives a memory access request including a virtual address, and selects one of the 2 N compressed data regions and one of the 2 N sets of free memory lists based on a modulus of the virtual address and 2 N . The compression circuit retrieves an abbreviated physical address corresponding to the virtual address from the metadata circuit, and performs a memory access operation on a memory block associated with the abbreviated physical address in the selected compressed data region.

公开(公告)号：WO2016167912A1

公开(公告)日：2016-10-20

申请号：PCT/US2016/022435

申请日：2016-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： PODAIMA, Jason Edward ,  WIERCIENSKI, Paul Christopher John ,  MIRETSKY, Alexander

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/1027 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/1036 ,  G06F2212/1021 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/50 ,  G06F2212/652 ,  G06F2212/654 ,  G06F2212/683

Abstract: A comparand that includes a virtual address is received. Upon determining a match of the comparand to a burst entry tag, a candidate matching translation data unit is selected. The selecting is from a plurality of translation data units associated with the burst entry tag, and is based at least in part on at least one bit of the virtual address. Content of the candidate matching translation data unit is compared to at least a portion of the comparand. Upon a match, a hit is generated.

Abstract translation: 收到包含虚拟地址的比较。 在确定比较与突发条目标签的匹配时，选择候选匹配翻译数据单元。 所述选择来自与所述突发条目标签相关联的多个翻译数据单元，并且至少部分地基于所述虚拟地址的至少一个位。 将候选匹配翻译数据单元的内容与比较的至少一部分进行比较。 比赛结束后，会产生命中。

公开(公告)号：WO2016126349A1

公开(公告)日：2016-08-11

申请号：PCT/US2015/067937

申请日：2015-12-29

Applicant: INTEL CORPORATION

Inventor： HARRIMAN, David J.

IPC: G06F12/10 ,  G06F12/08 ,  G06F9/455

CPC classification number: G06F12/1036 ,  G06F9/45558 ,  G06F12/1009 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2212/152

Abstract: Address remapping technologies are described. A method can include receiving, at a paging device of a system memory, a first physical address of an input/output (IO) device from a sub-page translator, where a sub-page location indicator may be associated with the first physical address. The method can further include identifying a virtual address in a sub-page translation table based on the physical address when the sub-page location indicator may be set to a sub-page lookup mode. The method can further include determining when to lookup the physical address in a sub-page translation table based on the sub-page location indicator. The method can further include communicating, to a virtual machine, the virtual address.

Abstract translation: 描述地址重映射技术。 一种方法可以包括在系统存储器的寻呼设备处从子页面转换器接收输入/输出（IO）设备的第一物理地址，其中子页面位置指示符可以与第一物理地址相关联 。 该方法还可以包括当子页面位置指示符可以被设置为子页面查找模式时，基于物理地址来识别子页面转换表中的虚拟地址。 该方法还可以包括基于子页面位置指示符确定何时在子页面转换表中查找物理地址。 该方法还可以包括向虚拟机通信虚拟地址。

公开(公告)号：WO2016016605A1

公开(公告)日：2016-02-04

申请号：PCT/GB2015/051809

申请日：2015-06-22

Applicant: ARM LIMITED

Inventor： HANSSON, Andreas ,  SAIDI, Ali Ghassan ,  UDIPI, Aniruddha Nagendran ,  DIESTELHORST, Stephan

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/0862 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/651 ,  G06F2212/654 ,  G06F2212/657 ,  G06F2212/681 ,  G06F2212/684 ,  Y02D10/13

Abstract: A data processing apparatus and method are provided for performing address translation in response to a memory access request issued by processing circuitry of the data processing apparatus and specifying a virtual address for a data item. Address translation circuitry performs an address translation process with reference to at least one descriptor provided by at least one page table, in order to produce a modified memory access request specifying a physical address for the data item. The address translation circuitry includes page table walk circuitry configured to generate at least one page table walk request in order to retrieve the at least one descriptor required for the address translation process. In addition, walk ahead circuitry is located in a path between the address translation circuitry and a memory device containing the at least one page table. The walk ahead circuitry comprises detection circuitry used to detect a memory page table walk request generated by the page table walk circuitry of the address translation circuitry for a descriptor in a page table. In addition, the walk ahead circuitry has further request generation circuitry which is used to generate a prefetch memory request in order to prefetch data from the memory device at a physical address determined with reference to the descriptor requested by the detected memory page table walk request. This prefetched data may be another descriptor required as part of the address translation process, or may be the actual data item being requested by the processing circuitry. Such an approach can significantly reduce latency associated with the address translation process.

Abstract translation: 提供了一种数据处理装置和方法，用于响应由数据处理装置的处理电路发出的存储器访问请求并指定数据项的虚拟地址来执行地址转换。 参考由至少一个页表提供的至少一个描述符，地址转换电路执行地址转换过程，以便产生指定数据项的物理地址的经修改的存储器访问请求。 地址转换电路包括页表行走电路，其被配置为生成至少一个页表步行请求，以便检索地址转换处理所需的至少一个描述符。 此外，前进电路位于地址转换电路和包含至少一个页表的存储器件之间的路径中。 步行电路包括用于检测由页表中的描述符的地址转换电路的页表步行电路产生的存储器页表行走请求的检测电路。 另外，步行电路具有进一步的请求生成电路，其用于生成预取存储器请求，以便以参考由检测到的存储器页表步行请求所请求的描述符确定的物理地址从存储器设备预取数据。 该预取数据可以是作为地址转换处理的一部分所需的另一个描述符，或可以是由处理电路请求的实际数据项。 这种方法可以显着减少与地址转换过程相关联的延迟。

公开(公告)号：WO2015153645A1

公开(公告)日：2015-10-08

申请号：PCT/US2015/023641

申请日：2015-03-31

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： VAHIDSAFA, Ali ,  CHEUNG, Connie, Wai Mun

IPC: G06F12/06 ,  G06F3/06 ,  G06F11/20

CPC classification number: G06F11/2094 ,  G06F3/0647 ,  G06F11/141 ,  G06F11/20 ,  G06F11/2069 ,  G06F12/0646 ,  G06F12/1036 ,  G06F2212/656

Abstract: A method for memory migration between addressing schemes, including: receiving a first request to access a first memory address and a second request to access a second memory address; comparing the first memory address and the second memory address with a barrier pointer referencing a barrier address and separating migrated addresses and un- migrated addresses; tagging the first request with a first tag indicative of the first addressing scheme in response to the first memory address being on an un-migrated side of the barrier address; tagging the second request with a second tag indicative of the second addressing scheme in response to the second memory address being on a migrated side of the barrier address; and sending the first request to a first memory controller unit (MCU) and the second request to a second MCU.

Abstract translation: 一种用于寻址方案之间的存储器迁移的方法，包括：接收访问第一存储器地址的第一请求和访问第二存储器地址的第二请求; 将第一存储器地址和第二存储器地址与引用屏障地址的屏障指针进行比较，并分离迁移的地址和未迁移的地址; 响应于所述第一存储器地址位于所述屏障地址的未迁移侧，用指示所述第一寻址方案的第一标签来标记所述第一请求; 响应于所述第二存储器地址位于所述屏障地址的迁移侧，用指示所述第二寻址方案的第二标签来标记所述第二请求; 并将第一请求发送到第一存储器控制器单元（MCU），并将第二请求发送给第二MCU。