公开(公告)号：US07928579B2

公开(公告)日：2011-04-19

申请号：US11588977

申请日：2006-10-27

Applicant: James M. Wark ,  Syed S. Ahmad

Inventor： James M. Wark ,  Syed S. Ahmad

IPC: H01L23/02 ,  H01L23/34 ,  H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/49827 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/0029 ,  H05K3/0041 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09836 ,  H01L2924/00

Abstract: Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. The vias are formed within the substrate to have a longitudinal axis sloped at an angle with respect to a reference line extending perpendicular to the first surface and the second surface of the substrate. The vias may be formed from the first surface to the opposing second surface, or the via may be formed as a first blind opening from the first surface, then a second opening may be formed from the second surface to be aligned with the first opening. Vias may be formed completely through a first substrate and a second substrate, and the substrates may be bonded together. Semiconductor devices including the vias of the present invention are also disclosed. A method of forming spring-like contacts is also disclosed.

Abstract translation: 公开了形成通孔的方法。 所述方法包括提供具有第一表面和相对的第二表面的基底。 通孔形成在衬底内，以具有相对于垂直于衬底的第一表面和第二表面延伸的参考线成一定角度倾斜的纵向轴线。 通孔可以由第一表面形成到相对的第二表面，或者通孔可以从第一表面形成为第一盲孔，然后可以从第二表面形成第二开口以与第一开口对准。 可以通过第一基板和第二基板完全形成通孔，并且基板可以结合在一起。 还公开了包括本发明的通孔的半导体器件。 还公开了一种形成弹簧状触点的方法。

公开(公告)号：US20080314863A1

公开(公告)日：2008-12-25

申请号：US12203081

申请日：2008-09-02

Applicant: Young Woo Kim ,  Byoung Youl Min ,  Chang Myung Ryu ,  Woo Lim Chae ,  Han Kim

Inventor： Young Woo Kim ,  Byoung Youl Min ,  Chang Myung Ryu ,  Woo Lim Chae ,  Han Kim

IPC: C23F1/00

CPC classification number: H05K1/162 ,  H05K3/0047 ,  H05K3/427 ,  H05K2201/0187 ,  H05K2201/09645 ,  H05K2201/09836 ,  H05K2201/09981 ,  H05K2203/1476 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: Disclosed is a PCB including an embedded capacitor and a method of fabricating the same. The long embedded capacitor is formed through an insulating layer, making a high capacitance and various capacitance designs possible.

Abstract translation: 公开了一种包括嵌入式电容器的PCB及其制造方法。 长的嵌入式电容器通过绝缘层形成，使得高电容和各种电容设计成为可能。

公开(公告)号：US07435913B2

公开(公告)日：2008-10-14

申请号：US11475479

申请日：2006-06-26

Applicant: Chin Hui Chong ,  Choon Kuan Lee

Inventor： Chin Hui Chong ,  Choon Kuan Lee

IPC: H01R12/04 ,  H05K1/00

CPC classification number: H01R12/526 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09836 ,  Y10T29/49147 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/4921 ,  Y10T29/49211 ,  Y10T29/4922

Abstract: Circuit boards, microelectronic devices, and other apparatuses having slanted vias are disclosed herein. In one embodiment, an apparatus for interconnecting electronic components includes a dielectric portion having a first surface and a second surface. A first terminal is disposed on the first surface of the dielectric portion for connection to a first electronic component. A second terminal is disposed on the second surface of the dielectric portion for connection to a second electronic component. The apparatus further includes a passage extending through the dielectric portion along a longitudinal axis oriented at an oblique angle relative to the first surface. The passage is at least partially filled with conductive material electrically connecting the first terminal to the second terminal.

Abstract translation: 本文公开了具有倾斜通孔的电路板，微电子器件和其它设备。 在一个实施例中，用于互连电子部件的装置包括具有第一表面和第二表面的电介质部分。 第一端子设置在电介质部分的第一表面上，用于连接到第一电子部件。 第二端子设置在电介质部分的第二表面上，用于连接到第二电子部件。 该装置还包括沿着相对于第一表面以倾斜角定向的纵向轴线延伸通过电介质部分的通道。 该通道至少部分地填充有将第一端子与第二端子电连接的导电材料。

公开(公告)号：US20070131452A1

公开(公告)日：2007-06-14

申请号：US11297303

申请日：2005-12-08

Applicant: Don Gilliland

Inventor： Don Gilliland

IPC: H05K7/06

CPC classification number: H05K1/115 ,  H05K1/0216 ,  H05K2201/09245 ,  H05K2201/09836 ,  Y10T29/49167

Abstract: A printed circuit board having via arrangements for reducing crosstalk is disclosed. The printed circuit board includes a first layer and a second layer. The printed circuit board also includes a first via and a second via, both traveling from the first layer to the second layer. The first via is orthogonal to the second via in a three dimensional space. In addition, the printed circuit board may include a third via traveling from the first layer to the second layer, and the third via is orthogonal to the first and second vias in the three dimensional space.

Abstract translation: 公开了一种具有用于减少串扰的通孔装置的印刷电路板。 印刷电路板包括第一层和第二层。 印刷电路板还包括从第一层传播到第二层的第一通孔和第二通孔。 第一通孔在三维空间中与第二通孔正交。 此外，印刷电路板可以包括从第一层传播到第二层的第三通孔，并且第三通孔与三维空间中的第一和第二通孔正交。

公开(公告)号：US20050269687A1

公开(公告)日：2005-12-08

申请号：US11145948

申请日：2005-06-07

Applicant: Robert Forcier

Inventor： Robert Forcier

IPC: B81B7/00 ,  B81B7/02 ,  G02B6/43 ,  H01L21/60 ,  H01L23/31 ,  H01L23/433 ,  H01L23/538 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H01L23/12

CPC classification number: H05K1/185 ,  B81C1/0023 ,  G02B6/43 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L2223/6677 ,  H01L2224/02333 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/0274 ,  H05K1/115 ,  H05K1/186 ,  H05K2201/09836 ,  H05K2203/061 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/3512

Abstract: A build-up structure for chip to chip interconnects and System-In-Package utilizing multi-angle vias for electrical and optical routing or bussing of electronic information and controlled CTE dielectrics including mesocomposites to achieve optimum electrical and optical performance of monolithic structures. Die, multiple die, Microelectromechanical Machines (MEMs) and/or other active or passive components such as transducers or capacitors can be accurately positioned on a substrate such as a copper heatsink and multi-angle stud bumps can be placed on the active sites of the components. A first dielectric layer is preferably placed on the components, thereby embedding the components in the structure. Through various processes of photolithography, laser machining, soft lithography or anisotropic conductive film bonding, escape routing and circuitry is formed on the first metal layer. Additional dielectric layers and metal circuitry are formed utilizing multi-angle vias to form escape routing from tight pitch bond pads on the die to other active and passive components. Multi-angle vias can carry electrical or optical information in the form of digital or analog electromagnetic current, or in the form of visible or non-visible optical bussing and interconnections.

公开(公告)号：US06946329B2

公开(公告)日：2005-09-20

申请号：US10832845

申请日：2004-04-27

Applicant: Mark Vincent Pierson ,  Jennifer Rebecca Sweterlitsch ,  Charles Gerard Woychik ,  Thurston Bryce Youngs, Jr.

Inventor： Mark Vincent Pierson ,  Jennifer Rebecca Sweterlitsch ,  Charles Gerard Woychik ,  Thurston Bryce Youngs, Jr.

IPC: H01L23/498 ,  H01R13/24 ,  H05K3/34 ,  H05K3/42 ,  H05K7/10 ,  H05K13/04 ,  H01L21/60 ,  H05K1/02

CPC classification number: H01R12/52 ,  H01L23/49827 ,  H01L2924/0002 ,  H01R12/57 ,  H01R13/2414 ,  H05K3/3436 ,  H05K3/42 ,  H05K7/1061 ,  H05K13/0465 ,  H05K2201/0133 ,  H05K2201/09836 ,  H05K2201/10378 ,  Y02P70/613 ,  Y10T29/49124 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A flexible, compliant layer of a single low modulus material for connecting a chip die directly to a circuit card without encapsulation. The flexible compliant layer provides stress relief caused by CTE thermal mismatch in chip die and circuit card. An array of copper plated vias are formed in said compliant layer with each via terminating on opposing surfaces of the layer in copper pads. Rather than copper, other metals, such as gold or nickel, may also be used. An array of holes may be positioned between said array of vias to provide additional resiliency. The plated vias may be angled with respect to said opposing surfaces to allow additional vertical and horizontal stress relief. Connection of the pads on one surface to high melt C-4 solder balls or columns on a chip die results in solder filled vias. Low melt solder connection of the pads on the other surface to a circuit card allows non-destructive rework of the cards.

Abstract translation: 用于将芯片裸片直接连接到电路卡而不封装的单个低模量材料的柔性兼容层。 灵活的柔性层提供了芯片和电路卡中CTE热失配引起的应力消除。 在所述顺应层中形成镀铜通孔的阵列，每个通孔终止于铜衬垫的相对表面上。 而不是铜，也可以使用其他金属，例如金或镍。 一组孔可以位于所述通孔阵列之间以提供额外的弹性。 电镀通孔可以相对于所述相对的表面成角度，以允许额外的垂直和水平应力释放。 将一个表面上的焊盘与芯片模具上的高熔点C-4焊球或柱的连接导致焊料填充的通孔。 将另一个表面上的焊盘的低熔点焊接连接到电路卡允许卡的非破坏性返修。

公开(公告)号：US06919508B2

公开(公告)日：2005-07-19

申请号：US10704131

申请日：2003-11-10

Applicant: Robert Forcier

Inventor： Robert Forcier

IPC: B81B7/00 ,  B81B7/02 ,  G02B6/43 ,  H01L21/60 ,  H01L23/31 ,  H01L23/433 ,  H01L23/538 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H01L23/02

CPC classification number: H05K1/185 ,  B81C1/0023 ,  G02B6/43 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L2223/6677 ,  H01L2224/02333 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/0274 ,  H05K1/115 ,  H05K1/186 ,  H05K2201/09836 ,  H05K2203/061 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/3512

Abstract: A build-up structure for chip to chip interconnects and System-In-Package utilizing multi-angle vias for electrical and optical routing or bussing of electronic information and controlled CTE dielectrics including mesocomposites to achieve optimum electrical and optical performance of monolithic structures. Die, multiple die, Microelectromechanical Machines (MEMs) and/or other active or passive components such as transducers or capacitors can be accurately positioned on a substrate such as a copper heatsink and multi-angle stud bumps can be placed on the active sites of the components. A first dielectric layer is preferably placed on the components, thereby embedding the components in the structure. Through various processes of photolithography, laser machining, soft lithography or anisotropic conductive film bonding, escape routing and circuitry is formed on the first metal layer. Additional dielectric layers and metal circuitry are formed utilizing multi-angle vias to form escape routing from tight pitch bond pads on the die to other active and passive components. Multi-angle vias can carry electrical or optical information in the form of digital or analog electromagnetic current, or in the form of visible or non-visible optical bussing and interconnections.

Abstract translation: 用于芯片到芯片互连的集成结构和利用多角度通孔的系统级封装，用于电和光路由或电子信息的总线以及包括中间复合材料的受控CTE电介质，以实现单片结构的最佳电气和光学性能。 芯片，多芯片，微机电（MEM）和/或其他有源或无源元件如换能器或电容器可以准确地定位在诸如铜散热片的基板上，并且可以将多角螺柱凸块放置在 组件。 第一电介质层优选地放置在部件上，从而将部件嵌入结构中。 通过光刻，激光加工，软光刻或各向异性导电膜接合的各种工艺，在第一金属层上形成逃逸路线和电路。 使用多角度通孔形成附加介电层和金属电路，以形成从芯片上的紧密间距接合焊盘到其它有源和无源部件的逃逸路由。 多角度通孔可以以数字或模拟电磁电流的形式携带电或光信息，或以可见或不可见的光学总线和互连的形式。

公开(公告)号：US20050125997A1

公开(公告)日：2005-06-16

申请号：US10495564

申请日：2002-11-14

Applicant: Juergen Usner ,  Ando Welling

Inventor： Juergen Usner ,  Ando Welling

IPC: B26D7/27 ,  B26F1/18 ,  B26F1/22 ,  G06K19/077 ,  H05K3/00 ,  H05K3/40 ,  H05K3/36 ,  B23P23/00

CPC classification number: G06K19/0775 ,  B26D7/27 ,  B26F1/18 ,  B26F1/22 ,  G06K19/077 ,  H05K3/4084 ,  H05K2201/09081 ,  H05K2201/09836 ,  H05K2203/0195 ,  H05K2203/081 ,  H05K2203/082 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49135 ,  Y10T29/49156 ,  Y10T29/5136 ,  Y10T29/5148 ,  Y10T29/5313 ,  Y10T83/0207

Abstract: A method and apparatus for through-contacting flexible substrates 1, in particular circuit boards, having electrically conductive contact zones 4, 41 present on two opposing surfaces 1a, 1b of the substrate provides that a cut 11 is produced obliquely to the surfaces of the substrate in the area of the contact zones, and the two substrate areas 20, 30 adjoining the oblique cut are moved past each other until they lock behind each other. Moving them past each other is effected by a ram 12, by the action of compressed air 13, by applying a vacuum 14 or by a driving hook 15 fixed to the cutting tool. The two steps of producing the cut and moving the two substrate areas adjoining the cut past each other are effected in a common processing station, preferably in a single operation.

Abstract translation: 存在于基板的两个相对表面1a，1b上的具有导电接触区域41,41的柔性基板1，特别是电路板的通过接触的方法和装置提供了一种切口11，其倾斜于 接触区域中的基板和与倾斜切口相邻的两个基板区域20,30彼此移动，直到它们彼此锁定。 通过压头空气13的作用，通过施加真空14或固定在切割工具上的驱动钩15，通过柱塞12进行移动。 在共同的处理站中，优选地在单个操作中实现产生切割和移动邻接切割的两个基板区域的两个步骤。

公开(公告)号：US20040095214A1

公开(公告)日：2004-05-20

申请号：US10298434

申请日：2002-11-18

Inventor： C. Allen Marlow ,  Jay DeAvis Baker ,  Lawrence Leroy Kneisel ,  Rosa Lynda Nuno ,  William David Hopfe

IPC: H01P005/00

CPC classification number: H01P5/184 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/15192 ,  H05K1/0272 ,  H05K1/0284 ,  H05K1/115 ,  H05K2201/09018 ,  H05K2201/09836

Abstract: The present invention consists of an electrical communications device including a three-dimensional substrate and a plurality of electrical devices attached thereto. The substrate is preferably a dielectric. The electrical device is preferably of the sort needed to conduct high frequency communications, such as a microwave antenna and photonic receivers and transmitters. The electrical devices are attached to the substrate at the connection points described by the intersection of a series vias and one of the substrate surfaces. The electrical devices are attached to the substrate in numerous ways, including solder, flipped chip ball bonds, wire bonds, or a gold stud assembly. In particular, the gold stud assembly is utilized to attach the antenna to the substrate, thereby providing a predetermined air gap therebetween.

Abstract translation: 本发明由包括三维基板和附接到其上的多个电气装置的电气通信装置组成。 基板优选为电介质。 电气设备优选地是进行高频通信所需的类型，例如微波天线和光子接收器和发射器。 在由串联通孔和一个基板表面的交叉点所描述的连接点处将电气装置附接到基板。 电气设备以多种方式附接到基板，包括焊料，翻转芯片球接合，引线接合或金螺柱组件。 特别地，金螺柱组件用于将天线附接到基板，从而在其间提供预定的气隙。

公开(公告)号：US6680534B2

公开(公告)日：2004-01-20

申请号：US97494701

申请日：2001-10-10

Applicant: MICRON TECHNOLOGY INC

Inventor： KINSMAN LARRY D

IPC: H01L23/498 ,  H05K1/11 ,  H05K3/46 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K1/115 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/0949 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/09945 ,  H01L2924/00

Abstract: The present invention is directed to an apparatus and method for connecting integrated circuits placed on opposite sides of a circuit board through utilization of conduction elements embedded in the circuit board and extending from one surface of the board to the other. Conductive traces extend along the surface of the circuit board from the conduction elements to the integrated circuits. The conductive traces may be formed from multiple conductive layers.

Abstract translation: 本发明涉及一种用于连接放置在电路板的相对侧上的集成电路的装置和方法，该集成电路通过利用嵌入电路板中的导电元件并从板的一个表面延伸到另一个表面。 导电迹线沿着电路板的表面从导电元件延伸到集成电路。 导电迹线可以由多个导电层形成。