COMPLETELY MUTUAL CONNECTION TYPE ASYNCHRONOUS TRANSFER MODE EXCHANGE DEVICE

    公开(公告)号:JPH09181742A

    公开(公告)日:1997-07-11

    申请号:JP28685196

    申请日:1996-10-29

    Abstract: PROBLEM TO BE SOLVED: To simplify the configuration of switch and a control method and to stably and easily execute control by outputting a cell, which is read out by an input cell selecting operation, through a bus dedicated to output under the control of switch module control means. SOLUTION: Plural switch output multiplexing means 20 are provided and this multiplexing means 20 performs the input cell selecting operation for inputting respective cells such as continuous cells containing cell data, cell enable signal (CEN), cell start signal (SOC) and synchronizing clock from an input port driving means 11 of plural line interface means 10, temporarily storing the inputted cells and afterwards, preferentially reading out the temporarily stored cells corresponding to the means 11 having high frequency of generation. Then, this read-out cell is outputted through a bus B3 dedicated to output under the control of switch module control means 70. Thus, the amount of hardware required for buffer configuration can be decreased.

    BYTE ALIGNING AND FRAME SYNCHRONIZING DEVICE

    公开(公告)号:JPH09181697A

    公开(公告)日:1997-07-11

    申请号:JP25002596

    申请日:1996-09-20

    Inventor: CHIYUN UOKU SUU

    Abstract: PROBLEM TO BE SOLVED: To improve byte aligning and frame synchronizing functions by applying output in the process of frame synchronization to byte alignment, surely preventing byte alignment errors and detecting frame synchronization loss and frame error states. SOLUTION: A data width extension circuit 10 extends input 8 parallel bits to 16 bits and the byte alignment is executed by a byte aligning circuit 20. A1A1/ A2A2 pattern detection circuits 119 and 129 detect successive two A1 and A2 bytes, either one is selected in a pattern selection circuit 140 and a successive pattern detection circuit 150 detects the successive 12 A1 and A2 frame patterns. A frame synchronization detection circuit 170 generates frame synchronizing signals FRSYNC, the abnormality of the frame synchronization is detected by a frame synchronization loss detection circuit 190 and a frame synchronization error detection circuit 180 and the byte aligning and frame synchronizing functions are improved.

    AUTOMATIC GENERATION METHOD OF REMOTE INSTRUCTION IN SATELLITE CONTROL SYSTEM USING INFERENCE UNIT

    公开(公告)号:JPH08272613A

    公开(公告)日:1996-10-18

    申请号:JP5519296

    申请日:1996-03-12

    Abstract: PROBLEM TO BE SOLVED: To unnecessitate a burden that an operator has to generate a remote instruction code (telecommand code) to enhance reliability and performance of a satellite control system. SOLUTION: A signal message processor 12 sends a lower remote instruction code and receives and preprocesses remote data from a satellite. A satellite task plan/analyzer 16 analyzes the remote data and a task and generates an upper remote instruction. A remote instruction generation/effector 15 has a remote instruction inference machine 17, retrieves data in a satellite operation knowledge base 18 and converts the upper remote instruction provided from the analyzer 16 into a mnemonic remote operation code. The effector 15 uses a remote instruction code data base 19, converts the mnemonic remote operation code into the lower remote instruction code and sends it to a satellite through the processor 12.

    NONINTERACTIVE ELECTRONIC SIGNATURE METHOD BASED ON PERSONALIDENTIFICATION INFORMATION WITH SELF-CERTIFICATION CHARACTERISTIC

    公开(公告)号:JPH08241036A

    公开(公告)日:1996-09-17

    申请号:JP789896

    申请日:1996-01-19

    Abstract: PROBLEM TO BE SOLVED: To provide a non-interactive electronic sign method based on personal identification information having self-certification characteristic, which has an advantage of a sign method based on a certifier and an advantage based on the personal identification information. SOLUTION: A system of a center is initialized, a result value based on a secret key and personal identification information are transmitted to the center, and after the verification information computed in the center is transmitted to a user, the user A selects a random number (r) to compute sign information (z) on a sign midium value (v), a hash function result value (e)=h(v, m) and a non-enciphered information in steps 24-26. In the step 27, the user A transmits a hash function (z, i, x, e) to a user B. In the steps 28-29, the user B calculates a hash function e'=h(v', m) to verify e=e'.

    SIGNAL RELAY EXCHANGE DUPLICATION CONTROL DEVICE AND METHOD

    公开(公告)号:JPH08186642A

    公开(公告)日:1996-07-16

    申请号:JP14498395

    申请日:1995-06-12

    Abstract: PURPOSE: To maintain consistency between a content of a database and data operated at present by installing two operating management sections in the system so as to allow other operating management section to conduct its function on the occurrence of a fault in the operating management section in service. CONSTITUTION: Two operating management sections 301, 302 are connected to a target system (SMX-1 system) and when the operating management section (OMM[P]) 301 is in operation, the other operating management section (OMM[S]) 302 is set in a standby state. HIFU(Highway Interface Unit) [P] 307, 308 and HIFU [S] boards 303, 304 are connected to the operating management sections 301, 302 so as to allow the system to be capable of coping with any system fault quickly. Furthermore, the operating management section 301, 302 are connected to a SIGNOS device 310 at a remote distance via a modem by means of the X.25 network. Even on the occurrence of a fault in the operating management section 301 (302) in service, the function is conducted by the other operating management section 302(301).

    HIGH-SPEED BIT SYNCHRONIZATION DEVICE WITH MANY-END CONTROL STRUCTURE

    公开(公告)号:JPH08163114A

    公开(公告)日:1996-06-21

    申请号:JP6734295

    申请日:1995-03-27

    Abstract: PURPOSE: To prevent a PLL loop gain from being sensitively chanted by a data bit pattern by providing a phase comparison gain limiter and avoiding gain limit of a phase comparator within a range of a transition occurrence frequency from NRZ data. CONSTITUTION: When a frequency synchronizing signal detector 25 outputs a frequency synchronizing signal, a phase difference output controller 26 provides an output of outputs UP, DP of a 1st phase frequency comparison gain controller 22 to a low pass filter 27, and when the detector 25 outputs no frequency synchronizing signal, no signal is given to the filter 27. When the frequency is not synchronized, the filter 27 applies low pass filtering only to outputs UF, DF of 2nd phase and frequency comparison gain limiters 24 and provides an output of only a low frequency component voltage including a DC component to a VCO 28. When the frequency is synchronized, the filter 27 applies low pass filtering to the outputs UP, DP of the gain limiter 22 and the outputs UF, DF of the limiters 24 respectively and the voltage of the low frequency component voltage including a DC component to the VCO 28. The VCO 28 uses an output voltage of the filter 27 to change the phase and the frequency of the output clock pulse.

    CERTIFICATION EXCHANGE AND ELECTRONIC SIGNATURE METHOD

    公开(公告)号:JPH07287515A

    公开(公告)日:1995-10-31

    申请号:JP7699295

    申请日:1995-03-31

    Abstract: PURPOSE: To provide a function for verifying the transmission/reception party confirmation of a transmission document and the alteration confirmation and transmission/reception action of the document itself by providing an authentication exchange method, with which the mutual value of a substance to be executed can be confirmed when processing and transmitting information, and signing the electric document. CONSTITUTION: This authentication exchange and electronic signature method is provided with a 1st step for setting (p), (q) and (g) ((p) and (q) are prime numbers, and (g) is an integer between '1' and (p) and the residual resulting from multiplying it by (q) and then dividing the result by (p) is 1) as system coefficients and a 2nd step for generating respective public keys from expressions, while each user uses (n) (n>=2) pieces of secret keys (s1 , s2 ...sn ) of integers between '1' and (q) as secret keys and uses (n) pieces of public keys (v1 , v2 ...vn ), as public keys corresponding to the secret keys.

    CONTROL METHOD FOR OVERLOAD ON DISTRIBUTED PROCESSOR IN FULL ELECTRONIC SWITCH BOARD

    公开(公告)号:JPH07203496A

    公开(公告)日:1995-08-04

    申请号:JP29147994

    申请日:1994-11-25

    Abstract: PURPOSE: To ensure services by automatically calculating a received call, and accepting only the calculated service call. CONSTITUTION: This device is provided with plural distributed alignment switching processors ASP 1 for sensing the generation of a transmission signal from a subscriber' s line and a trunk line, or taking charge of the alignment of incoming signals, and a number translation processor NTP 2 for translating the number of a transmission call and an input repeating call newly detected from the ASP 1, communicating it to the ASP which takes charge of an incoming call or an output repeating call for determining an incoming ASP and an output repeating ASP for setting the call. In the ASP 1, the subscriber's lines and the trunk lines are mounted so as to distributed, and a time switch, tone equipment, and signal equipment for call processing service are mounted. Thus, a process waiting limit value for adjusting the number of call processing processes in a waiting state is automatically calculated and applied so that the CPU use of a processor can be maximized at the time of limiting an over load, a control system for minimizing the limit of the service can be designated, and the stability of the service can be maintained even at the time of the over load of the ASP.

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