公开(公告)号：JPH08163114A

公开(公告)日：1996-06-21

申请号：JP6734295

申请日：1995-03-27

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： JIYU BOMU SUN ,  I BOMU CHIYORU ,  BAKU GON CHIYORU ,  GAN SOKI YORU

IPC: H03L7/00 ,  H03L7/083 ,  H03L7/087 ,  H03L7/14 ,  H03M5/06 ,  H04L7/033

Abstract: PURPOSE: To prevent a PLL loop gain from being sensitively chanted by a data bit pattern by providing a phase comparison gain limiter and avoiding gain limit of a phase comparator within a range of a transition occurrence frequency from NRZ data. CONSTITUTION: When a frequency synchronizing signal detector 25 outputs a frequency synchronizing signal, a phase difference output controller 26 provides an output of outputs UP, DP of a 1st phase frequency comparison gain controller 22 to a low pass filter 27, and when the detector 25 outputs no frequency synchronizing signal, no signal is given to the filter 27. When the frequency is not synchronized, the filter 27 applies low pass filtering only to outputs UF, DF of 2nd phase and frequency comparison gain limiters 24 and provides an output of only a low frequency component voltage including a DC component to a VCO 28. When the frequency is synchronized, the filter 27 applies low pass filtering to the outputs UP, DP of the gain limiter 22 and the outputs UF, DF of the limiters 24 respectively and the voltage of the low frequency component voltage including a DC component to the VCO 28. The VCO 28 uses an output voltage of the filter 27 to change the phase and the frequency of the output clock pulse.

公开(公告)号：JPH07170200A

公开(公告)日：1995-07-04

申请号：JP22032294

申请日：1994-09-14

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： I BOMU CHIYORU ,  IMU SON YORU ,  KIMU JIYON SHIKI

IPC: H03M13/00 ,  H03M13/09 ,  H03M13/33 ,  H04L1/00 ,  H04L7/00

Abstract: PURPOSE: To identify the boundary of a block only by performing the arithmetic operation of the newly added number of bytes or the number of bytes removed from the block, and outputs byte-synchronized and block-synchronized data before the starting point of the block. CONSTITUTION: A block synchronization identifying part 24 detects 8 syndrome outputs from an arithmetic part 23 with each byte time interval in a block synchronizing state. Then, when results whose remainders are 0 are outputted continuously (j) times from a syndrome output terminal, a block synchronizing state is declared, and the block synchronizing state is outputted. Also, when results whose remainders are not 0 are outputted continuously (i) times from the syndrome output terminal which detects the block synchronizing state, the block asynchronizing state is restored, and the state is outputted, and a byte unit detection process is executed. Moreover, the syndrome output which detects the block synchronizing state is identified, and outputted as 3 bit data so that a point of time when the remainder 0 is periodically outputted can be synchronized with the outputted byte interval.

公开(公告)号：JPH0646045A

公开(公告)日：1994-02-18

申请号：JP5866193

申请日：1993-03-18

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： I BOMU CHIYORU ,  BAKU GUON CHIYORU ,  BAKU HAN GU

IPC: H03L7/089 ,  H03L7/093 ,  H03L7/107 ,  H03L7/14 ,  H04L7/00 ,  H04L7/033

Abstract: PURPOSE: To stably restore NRZ data and clocks. CONSTITUTION: Even when not only PLL loop gain does not sensitively change, corresponding to a bit pattern and a bit speed of inputted NRZ data but also the NRZ data are not shifted and the range of the clock frequency change of a voltage-controlled oscillator 27 is large, the voltage-controlled oscillator 27 is made to oscillate so as to be synchronized with the multiple of the frequency of an external reference clock pulse REFCP. Thus, an NRZ data bit synchronization device for stably restoring the NRZ data and the clocks is obtained.