公开(公告)号：JPH08163114A

公开(公告)日：1996-06-21

申请号：JP6734295

申请日：1995-03-27

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： JIYU BOMU SUN ,  I BOMU CHIYORU ,  BAKU GON CHIYORU ,  GAN SOKI YORU

IPC: H03L7/00 ,  H03L7/083 ,  H03L7/087 ,  H03L7/14 ,  H03M5/06 ,  H04L7/033

Abstract: PURPOSE: To prevent a PLL loop gain from being sensitively chanted by a data bit pattern by providing a phase comparison gain limiter and avoiding gain limit of a phase comparator within a range of a transition occurrence frequency from NRZ data. CONSTITUTION: When a frequency synchronizing signal detector 25 outputs a frequency synchronizing signal, a phase difference output controller 26 provides an output of outputs UP, DP of a 1st phase frequency comparison gain controller 22 to a low pass filter 27, and when the detector 25 outputs no frequency synchronizing signal, no signal is given to the filter 27. When the frequency is not synchronized, the filter 27 applies low pass filtering only to outputs UF, DF of 2nd phase and frequency comparison gain limiters 24 and provides an output of only a low frequency component voltage including a DC component to a VCO 28. When the frequency is synchronized, the filter 27 applies low pass filtering to the outputs UP, DP of the gain limiter 22 and the outputs UF, DF of the limiters 24 respectively and the voltage of the low frequency component voltage including a DC component to the VCO 28. The VCO 28 uses an output voltage of the filter 27 to change the phase and the frequency of the output clock pulse.