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    RANDOMIZED TESTING WITHIN TRANSACTIONAL EXECUTION
    231.
    发明专利
    RANDOMIZED TESTING WITHIN TRANSACTIONAL EXECUTION 未知

    公开(公告)号：CA2928277A1

    公开(公告)日：2013-12-19

    申请号：CA2928277

    申请日：2013-05-03

    Applicant: IBM

    Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY

    IPC: G06F11/36 ,  G06F9/46

    Abstract: Task specific diagnostic controls are provided to facilitate the debugging of certain types of abort conditions. The diagnostic controls may be set to cause transactions to be selectively aborted, allowing a transaction to drive its abort handler routine for testing purposes. The controls include, for instance, a transaction diagnostic scope and a transaction diagnostic control. The transaction diagnostic scope indicates when the transaction diagnostic control is to be applied, and the transaction diagnostic control indicates whether transactions are to selectively aborted.

    COMPARE AND REPLACE DAT TABLE ENTRY
    232.
    发明专利
    COMPARE AND REPLACE DAT TABLE ENTRY 未知

    公开(公告)号：CA2874186A1

    公开(公告)日：2013-12-19

    申请号：CA2874186

    申请日：2012-11-26

    Applicant: IBM

    Inventor： GREINER DAN ,  ROGERS ROBERT

    IPC: G06F9/34 ,  G06F9/355

    Abstract: A first and a second operand are compared. If they are equal, the contents of register R1 + 1 are stored at the second-operand location, and the specified CPU or CPUs in the configuration are cleared of all TLB table entries of the designated type formed through the use of the replaced entry in storage, and all lower-level TLB table entries formed through the use of the cleared higher-level TLB table entries. A valid DAT table entry is replaced with a new entry, and the Translation Lookaside Buffer (TLB) is purged of any copies of (at least) the single entry on all CPUs in the configuration. If the first and second operands are unequal, the second operand is loaded at the first-operand location. The comparison result is indicated by the condition code. A method, system and a computer program product are provided.

    PROCESSOR ASSIST FACILITY
    233.
    发明专利
    PROCESSOR ASSIST FACILITY 未知

    公开(公告)号：CA2874184A1

    公开(公告)日：2013-12-19

    申请号：CA2874184

    申请日：2012-11-26

    Applicant: IBM

    Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN ,  RELSON PETER JEREMY ,  PHILLEY RANDALL WILLIAM

    IPC: G06F9/30

    Abstract: An operation is provided to signal a processor that action is to be taken to facilitate execution of a transaction that has aborted one or more times. The operation is specified within an instruction or is itself an instruction. The instruction is executed based on detecting an abort of the transactions, and includes a field indicating how many times the transaction has aborted. The processor uses this information to determine what action is to be taken.

    Traducción de direcciones de entrada/salida a direcciones de memoria
    235.
    发明专利
    Traducción de direcciones de entrada/salida a direcciones de memoria 未知

    公开(公告)号：ES2428822T3

    公开(公告)日：2013-11-11

    申请号：ES10776350

    申请日：2010-11-08

    Applicant: IBM

    Inventor： CRADDOCK DAVID ,  GREGG THOMAS ,  GREINER DAN ,  LAIS ERIC NORMAN

    IPC: G06F13/16 ,  G06F12/10

    Abstract: Un método de traducción de direcciones en un entorno informático, dicho método que comprende: obtener una dirección a partir de un adaptador (110) a ser traducida a una dirección de memoria directamenteutilizable en el acceso a la memoria del sistema del entorno informático, la dirección que comprende unapluralidad de bits, la pluralidad de bits que comprende una primera parte de bits y una segunda parte de bits;recibir un valor de intervalo de direcciones que indica un intervalo de direcciones permitidas, en donde elintervalo se define por una dirección base (214) y un límite (216) situado en una entrada de tabla de dispositivoasociada con el adaptador, la entrada de tabla de dispositivo (210) situada mediante un identificador solicitantesituado en una petición emitida por el adaptador; validar la dirección obtenida a partir del adaptador usando al menos la primera parte de bits y el intervalo dedirecciones recibido; y convertir la dirección obtenida a partir del adaptador a la dirección de memoria directamente utilizable en elacceso a la memoria del sistema del entorno informático, el método que se caracteriza por la conversión queignora la primera parte de bits y que usa la segunda parte de bits para obtener información de dirección a partirde uno o más niveles de tablas de traducción de direcciones para realizar la conversión.

    Translation of input/output addresses to memory addresses
    238.
    发明专利
    Translation of input/output addresses to memory addresses 未知

    公开(公告)号：AU2010355813A1

    公开(公告)日：2012-12-20

    申请号：AU2010355813

    申请日：2010-11-08

    Applicant: IBM

    Inventor： CRADDOCK DAVID ,  GREGG THOMAS ,  GREINER DAN ,  LAIS ERIC NORMAN

    IPC: G06F13/16 ,  G06F12/10

    Abstract: An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.

    Non-quiescing key setting facility
    239.
    发明专利
    Non-quiescing key setting facility 未知

    公开(公告)号：GB2488458A

    公开(公告)日：2012-08-29

    申请号：GB201207328

    申请日：2010-12-14

    Applicant: IBM

    Inventor： SLEGEL TIMOTHY ,  GREINER DAN ,  SHUM CHUNG-LUNG KEVIN ,  JACOBI CHRISTIAN

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/14

    Abstract: A non-quiescing key setting facility is provided that enables manipulation of storage keys to be performed without quiescing operations of other processors of a multiprocessor system. With this facility, a storage key, which is accessible by a plurality of processors of the multiprocessor system, is updated absent a quiesce of operations of the plurality of processors. Since the storage key is updated absent quiescing of other operations, the storage key may be observed by a processor as having one value at the start of an operation performed by the processor and a second value at the end of the operation. A mechanism is provided to enable the operation to continue, avoiding a fatal exception.

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