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公开(公告)号：DE60027339D1
公开(公告)日：2006-05-24
申请号：DE60027339
申请日：2000-02-17
Applicant: ST MICROELECTRONICS INC
Inventor： GURITZ ELMER HENRY
IPC: G11C11/407 , G11C11/409 , G05F1/46 , G05F3/24 , G11C5/14 , G11C7/14 , G11C11/404 , G11C11/4074 , G11C11/4099 , H01L21/822 , H01L27/04
Abstract: A reference voltage generator includes a voltage divider connected to a voltage supply and a feedback buffer amplifier. The divider supplies at least one voltage output signal to the feedback buffer amplifier under control of a feedback control signal supplied by the feedback buffer amplifier. The reference voltage generator may include a delay element coupled between the voltage divider and the feedback buffer amplifier in-line with the feedback control signal and a low impedance output buffer that receives the voltage output signal from the voltage divider and supplies the reference voltage at an output node. The reference voltage may be supplied to the reference plates of bit storage capacitors within the memory cells. The storage capacitors can be protected by including a clamping circuit that maintains the output node at a voltage between the voltages of the two voltage supply terminals.
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公开(公告)号：DE69534542D1
公开(公告)日：2005-12-01
申请号：DE69534542
申请日：1995-07-11
Applicant: ST MICROELECTRONICS INC
Inventor： CHAN TSIU C , HUANG KUEI-WU
IPC: H01L21/28 , H01L21/768 , H01L21/60
Abstract: A method is provided for forming an improved contact opening of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Planarization of the semiconductor structure is maximized and misalignment of contact openings is tolerated by first forming a conductive structure over a portion of a first body. A thin dielectric layer is formed at least partially over the conductive structure. A thick film, having a high etch selectivity to the thin dielectric layer, is formed over the dielectric layer. The thick film is patterned and etched to form a stack substantially over the conductive structure. An insulation layer is formed over the thin dielectric layer and the stack wherein the stack has a relatively high etch selectivity to the insulation layer. The insulation layer is etched back to expose an upper surface of the stack. The stack is then etched to form an opening in the insulation layer exposing the thin dielectric layer which acts as an etch stop during the stack etch process. The thin dielectric layer is then etched in the opening to expose the first conductive layer. A conductor is then formed in the opening contacting the underlying conductive structure. The thin dielectric under the insulation layer and on the sides of the opening near the conductive structure will increase the distance and help to electrically isolate the conductor at the edge of the contact opening from nearby active areas and devices.
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公开(公告)号：DE69635008D1
公开(公告)日：2005-09-08
申请号：DE69635008
申请日：1996-04-30
Applicant: ST MICROELECTRONICS INC
Inventor： EDWARDS WILLIAM ERNEST
Abstract: A voltage regulator with load pole stabilization is disclosed. The voltage regulator consists of an output stage, a comparator stage, and an active load. The active load draws current from the output of the voltage regulator inversely proportional to the current demand on the voltage regulator. When the output current demand is large, the active load draws relatively low current. When the output current demand is large, the active load draws a relatively large amount of current. Consequently, the disclosed voltage regulator has high stability without consuming excess power.
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公开(公告)号：DE69634376D1
公开(公告)日：2005-03-31
申请号：DE69634376
申请日：1996-04-24
Applicant: ST MICROELECTRONICS INC
Inventor： HUNDT MICHAEL J , CHIU ANTHONY M
Abstract: A socketed integrated circuit packaging system, including a packaged integrated circuit and a socket therefor, is disclosed. The integrated circuit package includes a device circuit board to which a thermally conductive slug is mounted; the underside of the device circuit board has a plurality of lands arranged in an array. The integrated circuit chip is mounted to the slug, through a hole in the device circuit board, and is wire-bonded to the device circuit board and thus to the lands on the underside. The socket is a molded frame, having a hole therethrough to receive the conductive slug of the integrated circuit package; the socket may also have its own thermally conductive slug disposed within the hole of the frame. The socket has spring contact members at locations matching the location of the lands on the device circuit board. The integrated circuit package may be inserted into the socket frame, held there by a metal or molded clip. A low profile, low cost, and high thermal conductivity package and socket combination, is thus produced.
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公开(公告)号：DE69633652T2
公开(公告)日：2005-03-03
申请号：DE69633652
申请日：1996-05-13
Applicant: ST MICROELECTRONICS INC
Inventor： YIN RONG
IPC: H03K19/00 , H03K19/017
Abstract: A low power, low voltage level shifter is provided. The voltage level shifter includes a first switching circuit, and a second switching circuit. The first switching circuit has a first input terminal for receiving a first oscillating signal, and based on the first oscillating signal, switches the output of the first switching circuit between a first voltage level and a second voltage level. The second switching circuit has a second input terminal connected to the output terminal of the first switching circuit. The second switching circuit also has a third input terminal for receiving a second oscillating signal which is out of phase with the first oscillating signal. Based on the input signals received, the second switching circuit generates an output signal that switches between a third voltage level and a fourth voltage level at a selected rate and frequency.
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Patent Agency Ranking
公开(公告)号：DE69727904T2
公开(公告)日：2005-02-03
申请号：DE69727904
申请日：1997-12-12
Applicant: ST MICROELECTRONICS INC
Inventor： PHILLIPS WILLIAM AIDAN
IPC: H01L27/04 , G05D3/12 , H01L21/822 , H01L27/08 , H02P7/288
Abstract: An integrated circuit motor controller (142) having two or more integrated resistor dividers (154,156) which produce signals to be compared with each other is disclosed. The circuit is designed to substantially reduce the dependency of the comparison on the reverse bias of the junctions between diffused resistors in the integrated resistor dividers and the silicon into which they are diffused.
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公开(公告)号：DE60107106D1
公开(公告)日：2004-12-16
申请号：DE60107106
申请日：2001-08-30
Inventor： FRUHAUF F , GOUPIL HERVE , LEYDIER ROBERT
Abstract: A dual-mode IC is provided for operating in first mode such as an ISO mode in accordance with International Standards Organization 7816 (ISO 7816) protocol, and a second, non-ISO mode, such as a USB mode in accordance with Universal Serial Bus (USB) protocol. The dual-mode IC is preferably in a smart card and includes a microprocessor, a switching block, and an external interface. The external interface includes a voltage supply pad, a reference voltage pad, a reset pad, a clock pad and an input/output pad in accordance with the ISO 7816 protocol, and a D-plus pad and D-minus pad in accordance with the USB protocol. The IC further includes a mode configuration circuit for detecting a USB mode condition on at least one of the D-plus and D-minus pads, and configuring the IC in the ISO mode or the USB mode depending on the result. Once the IC is configured in a particular mode, it will operate in only that mode until the next power-on reset sequence.
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公开(公告)号：DE69630257T2
公开(公告)日：2004-08-26
申请号：DE69630257
申请日：1996-04-10
Applicant: ST MICROELECTRONICS INC
Inventor： CHAN TSUI C , BRYANT FRANK R , NGUYEN LOI N , BALASINSKI ARTUR P
IPC: H01L21/28 , H01L21/285 , H01L21/60 , H01L21/768 , H01L23/485 , H01L23/528 , H01L27/11
Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.
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公开(公告)号：DE69233383D1
公开(公告)日：2004-08-26
申请号：DE69233383
申请日：1992-05-26
Applicant: ST MICROELECTRONICS INC
Inventor： CHAN TSUI C , BRYANT FRANK R , JORGENSON LISA K
IPC: H01L21/8244 , H01L27/11 , H01L21/82
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公开(公告)号：DE69824992D1
公开(公告)日：2004-08-19
申请号：DE69824992
申请日：1998-06-03
Applicant: ST MICROELECTRONICS INC
Inventor： PATTI GUISEPPE
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