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    SOLID STATE OPTICAL IMAGE PICKUP PIXEL WITH RESISTANT LOAD
    1.
    发明专利
    SOLID STATE OPTICAL IMAGE PICKUP PIXEL WITH RESISTANT LOAD 失效

    公开(公告)号：JP2000036586A

    公开(公告)日：2000-02-02

    申请号：JP17842599

    申请日：1999-06-24

    Applicant: ST MICROELECTRONICS INC

    Inventor： KALNITSKY ALEXANDER ,  BRYANT FRANK R ,  SABATINI MARCO

    IPC: H01L27/14 ,  H01L27/146 ,  H01L31/0352 ,  G01J1/44 ,  H04N5/335

    Abstract: PROBLEM TO BE SOLVED: To increase the optical filter of the pixel of a CMOS image array by providing a radiation-sensitive resistance element where an access transistor being located at a second level is connected to an access transistor being located at a second level. SOLUTION: The pixel of a passive-type pixel construct 300 has a substrate 301, and an MOS pass transistor 303 is formed on it. The transistor is provided with a source being formed in the substrate, drain diffusion regions 305 and 307, and a gate 308 being formed on the substrate. In a gate electrode, first and second capacitor plates 309 and 311 of two polysilicon constructs are provided at the upper part of the pass transistor 303. The first capacitor plate 309 is separated from the substrate 301 and the pass transistor 303 by a passivation layer 313. The second capacitor plate 311 is separated from the first capacitor plate 309 by a capacitor dielectric layer 315. A photosensitive resistance element 317 is provided in the inclusion layer of the second capacitor plate.

    2.
    发明专利
    未知

    公开(公告)号：DE69630257T2

    公开(公告)日：2004-08-26

    申请号：DE69630257

    申请日：1996-04-10

    Applicant: ST MICROELECTRONICS INC

    Inventor： CHAN TSUI C ,  BRYANT FRANK R ,  NGUYEN LOI N ,  BALASINSKI ARTUR P

    IPC: H01L21/28 ,  H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/528 ,  H01L27/11

    Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.

    5.
    发明专利
    未知

    公开(公告)号：DE69535348D1

    公开(公告)日：2007-02-08

    申请号：DE69535348

    申请日：1995-05-24

    Applicant: ST MICROELECTRONICS INC

    Inventor： HODGES ROBERT L ,  BRYANT FRANK R

    IPC: H01L21/76 ,  H01L21/762 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/32 ,  H01L21/768 ,  H01L21/8247 ,  H01L21/8248 ,  H01L23/522 ,  H01L29/51 ,  H01L29/78

    Abstract: A method is provided for forming an improved device dielectric of a semiconductor integrated circuit, and an integrated circuit formed according to the same. For scaling geometries for use in the submicron regime, a composite dielectric layer used as a device dielectric is formed over a plurality of active areas adjacent to a field oxide region. The composite dielectric layer is formed before the field oxide region is formed and comprises a non-porous silicon nitride layer. The non-porous silicon nitride layer preferably comprises a thin deposited silicon nitride layer overlying a thin nitridized region of the substrate. The silicon nitride layer is partially oxidized during the subsequent formation of a field oxide region between the plurality of active areas. An oxide layer may be formed over the silicon nitride layer before the formation of the field oxide region which will then be densified during the field oxide formation. The composite dielectric layer is then patterned and etched to form the dielectric portion of various integrated circuit devices.

    6.
    发明专利
    未知

    公开(公告)号：DE69734383D1

    公开(公告)日：2006-03-02

    申请号：DE69734383

    申请日：1997-12-12

    Applicant: ST MICROELECTRONICS INC

    Inventor： BRYANT FRANK R ,  SINGH ABHA R ,  CUNNINGHAM JAMES A

    IPC: H01L21/316 ,  H01L21/66 ,  H01L21/70 ,  H01L21/82 ,  H01L23/31 ,  H01L23/50

    Abstract: A passivation structure is formed using two passivation layers and a protective overcoat layer using two masking steps. The first passivation layer is formed over the wafer and openings are provided to expose portions of the pads for testing the device and fusible links. After testing and laser repair, a second passivation layer is formed over the wafer followed a deposit of the protective overcoat. The protective overcoat is patterned and etched, exposing the pads. The remaining portions of the protective overcoat are used as a mask to remove portions of the second passivation layer overlying the pads. Leads are then attached to pads and the devices are encapsulated for packaging. The second passivation layer overlaps edge portions of the first passivation layer at the bond pads to enhance moisture resistance.

    9.
    发明专利
    未知

    公开(公告)号：DE69630257D1

    公开(公告)日：2003-11-13

    申请号：DE69630257

    申请日：1996-04-10

    Applicant: ST MICROELECTRONICS INC

    Inventor： CHAN TSUI C ,  BRYANT FRANK R ,  NGUYEN LOI N ,  BALASINSKI ARTUR P

    IPC: H01L21/28 ,  H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/528 ,  H01L27/11

    Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.

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