公开(公告)号：EP1042868A1

公开(公告)日：2000-10-11

申请号：EP99955090.8

申请日：1999-10-20

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： BARNA, Paul

IPC: H03K19/0175

CPC classification number: H03K19/017509

Abstract: A variable low voltage signal translator uses a driver (12) for outputting a low voltage signal translation. A control circuit (18) is coupled to the driver (12) for enabling and disabling the driver (12) wherein the control circuit (18) has an input coupled to the signal to be translated. One terminal of the pull-up resistor (14) is coupled to an output of the driver (12). A second terminal of the pull-up resistor (14) is coupled to a voltage supply (16) which provides the low voltage level of the variable low voltage signal translator.

公开(公告)号：EP0967723A3

公开(公告)日：2000-08-23

申请号：EP98122505.5

申请日：1998-11-27

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： Wojewoda, Igor ,  Drake, Rodney J. ,  Boles, Brian E.

IPC: H03K19/173 ,  G06F1/22 ,  G06F12/06

CPC classification number: G06F1/22 ,  H03K19/173 ,  H03K19/1731

Abstract: The invention allows the programmer to designate one or more pins on a semiconductor device as either address pins, which are in addition to a predetermined set of address lines or as alternate I/O pins. The object of the invention is to provide the programmer with the capability of defining with preciseness the particular size of the address bus needed for a specific application. The invention is comprised of a programming port, optional programing logic, configuration logic, selection logic and a set of pins that may be configured as per the programmer's requirements. The invention is to exist on a single, monolithic semiconductor device.

公开(公告)号：EP0612422B1

公开(公告)日：2000-07-05

申请号：EP92924264.2

申请日：1992-11-12

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： BERMAN, Eric ,  ITALIANO, Greg ,  PADGAONKAR, Ajay ,  ALLEN, Ray

IPC: G06F11/20 ,  G11C29/00

CPC classification number: G06F9/30145 ,  G06F9/30167 ,  G06F11/2236 ,  G06F11/261 ,  G06F15/7814

Abstract: A microcontroller fabricated on a semiconductor chip has an on-chip EPROM program memory with programmable EPROM configuration fuses located in a limited number of addresses of the on-chip program memory, the condition of each of EPROM fuse being defined as blown or not blown according to the value of the bit stored in the respective address of the on-chip program memory. The operating modes of the microcontroller are configurable by appropriately programming at least some of the EPROM fuses. Testing of the microcontroller in at least some of the operating modes is achieved by using latches outside the program memory to emulate the EPROM fuses, while suppressing the capability to set the condition of the EPROM fuses during the testing. Upon completion of the testing, control of the operating modes of the microcontroller is returned to the EPROM fuses, and the latches are precluded from further emulating the EPROM fuses.

公开(公告)号：EP1000439A1

公开(公告)日：2000-05-17

申请号：EP99918816.2

申请日：1999-04-23

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： ST. AMAND, Roger ,  MA, Robert ,  DEUTSCHER, Neil

IPC: H01L21/762 ,  H01L21/32 ,  H01L21/314

CPC classification number: H01L21/3145 ,  H01L21/32 ,  H01L21/76202

Abstract: A method is disclosed for forming narrow thermal silicon dioxide side isolation regions in a semiconductor substrate and MOS or CMOS semiconductor devices fabricated by this method. A thin stress relief layer is used in conjunction with a polysilicon buffering stress relief layer on the surface of a semiconductor substrate prior to the field oxidation process to restrict lateral silicon dioxide expansion thereby permitting the creation of narrow thermal silicon dioxide side isolation regions in the semiconductor substrate. A silicon dioxide layer is also used between an amorphous polysilicon (buffering stress relief) layer and a silicon nitride layer to function as an oxide cap, to avoid undesired pitting of the amorphous polysilicon layer, and to avoid interaction between the silicon nitride and amorphous polysilicon layers in areas of high stress.

公开(公告)号：EP0905612A3

公开(公告)日：2000-04-26

申请号：EP98117770.2

申请日：1998-09-18

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： Drake, Rodney J. ,  Triece, Joseph W.

IPC: G06F9/30 ,  G06F9/32

CPC classification number: G06F9/30069 ,  G06F9/30149

Abstract: An instruction set for a microcontroller which has robust multiple word instructions. The instruction set has a plurality of instructions wherein the plurality of instructions comprises single word instructions and multiple word instructions. At least one bit is located in a predetermined location in all non-first words of all multiple word instructions. The bit will be decoded by the microcontroller as no operation bit if the first word of the multiple word instruction is not executed prior to execution of any succeeding words in the multiple word instruction.

公开(公告)号：EP0985266A1

公开(公告)日：2000-03-15

申请号：EP99912935.6

申请日：1999-03-24

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： BRUWER, Frederick ,  SMIT, Willem

IPC: H03B5/20

CPC classification number: H03B5/20 ,  H03B2201/02 ,  H03B2201/025 ,  H03B2201/0266 ,  H03J2200/10 ,  Y10T307/826

Abstract: A transmitter system comprises an oscillator and having an adjustable monolithic capacitor circuit used for frequency stabilization. The oscillator signal is modulated and transmitted. A data generating chip is coupled to the transmitter. The data generating chip is used for adjusting and controlling the transmitter oscillator frequency signal. The adjustable capacitor circuit is located internal to the data generating chip and is coupled to a ground pin and one of a plurality of function pins on the data generating chip. The adjustable capacitor circuit is used for adjusting and setting the centerpoint of the transmitter oscillator frequency signal.

公开(公告)号：EP0967723A2

公开(公告)日：1999-12-29

申请号：EP98122505.5

申请日：1998-11-27

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： Wojewoda, Igor ,  Drake, Rodney J. ,  Boles, Brian E.

IPC: H03K19/173

CPC classification number: G06F1/22 ,  H03K19/173 ,  H03K19/1731

Abstract: The invention allows the programmer to designate one or more pins on a semiconductor device as either address pins, which are in addition to a predetermined set of address lines or as alternate I/O pins. The object of the invention is to provide the programmer with the capability of defining with preciseness the particular size of the address bus needed for a specific application. The invention is comprised of a programming port, optional programing logic, configuration logic, selection logic and a set of pins that may be configured as per the programmer's requirements. The invention is to exist on a single, monolithic semiconductor device.

Abstract translation: 本发明允许编程器将半导体器件上的一个或多个引脚指定为除了预定的一组地址线之外的地址引脚或者作为替代的I / O引脚。 本发明的目的是为程序员提供精确地定义特定应用所需的地址总线的特定大小的能力。 本发明由编程端口，可选的编程逻辑，配置逻辑，选择逻辑和可根据编程者的要求进行配置的一组引脚组成。 本发明存在于单个单片半导体器件上。

公开(公告)号：EP0913766A3

公开(公告)日：1999-12-29

申请号：EP98119376.6

申请日：1998-10-14

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： Triece, Joseph W. ,  Mitra, Sumit K.

IPC: G06F9/34

CPC classification number: G06F9/30181 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/30192 ,  G06F9/34

Abstract: A system for allowing multiple addressing modes while maximizing a number of available opcodes and addressable registers. The system has a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses. The system has an instruction set having a plurality of instructions. Each instruction has a plurality of bits wherein none of the plurality of bits in each of the plurality of instructions are dedicated bits for implementing different addressing modes. Each of the plurality of instructions are able to implement different addressing modes by addressing the virtual register addresses in the processor architecture scheme. Since no bits are required for implementing different addressing modes, the length of the opcode field and the register address field are determined by the number of opcodes and the number of addressable registers the user wishes to implement.

公开(公告)号：EP0951733A1

公开(公告)日：1999-10-27

申请号：EP98956692.0

申请日：1998-11-10

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： LUNDY, Walter, E. ,  EICHMAN, Eric, C.

IPC: H01L21

CPC classification number: H01L23/53223 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A relatively low temperature metal deposition method is disclosed for reliably and completely filling with metal ohmic contact openings and/or via holes or openings between spaced apart metalization layers in a semiconductor structure. The method incorporates several process steps including depositing a layer of Titanium or Titanium based metal into the ohmic contact opening and/or via hole followed by successive depositions of a metal seed layer of an Aluminum based metal such as Aluminum Silicon Copper to partially fill the ohmic contact opening and/or via hole and a metal covering layer of an Aluminum based metal such as Aluminum Silicon Copper to completely fill the ohmic contact opening.

公开(公告)号：EP0923663A1

公开(公告)日：1999-06-23

申请号：EP98926219.0

申请日：1998-06-03

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： BRUWER, Frederick, J.

IPC: E05B49 ,  G07C9 ,  H04L9 ,  H04Q9

CPC classification number: G07C9/00182 ,  G07C9/00817 ,  G07C9/00857 ,  G07C2009/0023 ,  G07C2009/00253 ,  G07C2009/00769 ,  G07C2009/00928 ,  G07C2209/06 ,  H04L9/0869 ,  H04L2209/34 ,  H04L2209/80 ,  H04L2209/84

Abstract: A method and system for the remote control of devices having a secure self learn capability. The system includes an encoder (10) and a decoder (12), the encoder encoding variable information including a user key using a non-linear algorithm to produce an encoded value transmitted to the decoder, the decoder decoding the value using the same algorithm. In a learning mode a new encoder is to be added to the system. The new encoder produces an encoded value using a key generation seed. The decoder, upon receiving the encoded key generation seed, produces a decoding key based upon the decoded key generation seed. The decoding key is stored in the decoder memory allowing valid recognition of the new encoder in a secure manner.