MERGED PLATINUM SILICIDE FUSE AND SCHOTTKY DIODE AND METHOD OF MANUFACTURE THEREOF
    271.
    发明申请
    MERGED PLATINUM SILICIDE FUSE AND SCHOTTKY DIODE AND METHOD OF MANUFACTURE THEREOF 审中-公开
    合并的硅酸钠熔丝和肖特基二极管及其制造方法

    公开(公告)号:WO1983001866A1

    公开(公告)日:1983-05-26

    申请号:PCT/US1982001576

    申请日:1982-11-08

    CPC classification number: H01L23/5256 H01L29/872 H01L2924/0002 H01L2924/00

    Abstract: La structure fusionnée est formée par une couche isolante (11) présentant une ouverture sur un substrat de silicium (10). Une couche façonnée de polysilicium (12) repose sur la couche isolante et est en contact avec le substrat au travers de l'ouverture; une couche de siliciure de platine (16) ayant la même forme que les couches de polysilicium-PtSi en contact avec le substrat forme une diode Schottky (40) et la région sur la couche isolante forme le fusible. Cette structure fusionnée présente des caractéristiques électriques supérieures de diode Schottky et est plus compacte que les structures de l'art antérieur.

    A CURRENT SOURCE CIRCUIT
    272.
    发明申请
    A CURRENT SOURCE CIRCUIT 审中-公开
    电流源电路

    公开(公告)号:WO1983000397A1

    公开(公告)日:1983-02-03

    申请号:PCT/US1982000938

    申请日:1982-07-12

    CPC classification number: G05F3/227

    Abstract: Source de courant pour des régulateurs de tension utilisés dans des circuits intégrés logiques avec couplage d'émetteur (ECL) pour éliminer les variations du courant de sortie dues aux fluctuations dans la source de tension. Des transistors d'un type de polarité sont utilisés. Une source de courant (11) est connectée à un noeud de sortie (15). Un transistor (Q2) génère un courant proportionnel à la tension de sortie (15) pour développer une tension sur une résistance (12) commandant à son tour un transistor (Q3) en série avec une résistance (14) et un transistor connecté par diode (Q4). Par une action spéculaire du courant, le courant s'écoulant dans le transistor (Q4) est réfléchi (IQ1) par le transistor (Q1). Le courant de sortie (I0) est le courant s'écoulant au travers de la résistance (11) moins le courant (IQ1).

    METHOD AND APPARATUS FOR INSPECTION OF PIN GRID ARRAY PACKAGES FOR BENT LEADS
    273.
    发明申请
    METHOD AND APPARATUS FOR INSPECTION OF PIN GRID ARRAY PACKAGES FOR BENT LEADS 审中-公开
    用于检查用于弯曲引线的引脚网格阵列的方法和装置

    公开(公告)号:WO1999000836A1

    公开(公告)日:1999-01-07

    申请号:PCT/US1997022417

    申请日:1997-12-01

    CPC classification number: H01L22/12 Y10T29/53183

    Abstract: A pin grid array inspection device includes an inspection gauge having a rectangular matrix of holes corresponding to leads of a pin grid array. In the preferred embodiment, a retractable device holder extends through a central opening in the inspection gauge. The device holder contacts the central leadless section of the pin grid array and provides a resting place for the pin grid array before an alignment mechanism grasps the pin grid array. An alignment mechanism positioned above the inspection gauge guides the pin grid array and aligns it to the inspection gauge. The device holder retracts, and the pin grid array descends into the inspection gauge due to gravity. An optical scanning receiver is mounted opposite of an optical scanning transmitter to receive an optical inspection beam. The optical scanning transmitter shines an optical inspection beam over the pin grid array as it rests in the inspection gauge. A bent lead will cause friction with its corresponding hole in the inspection gauge causing the pin grid array to remain at least partially raised above the inspection gauge. If the pin grid array does not lie flatly in the inspection gauge, and is therefore at least partially raised above the inspection gauge, it blocks optical inspection beam, and an output circuit signals the automated operator that the pin grid array has at least one bent lead. If the pin grid array lies flatly in the inspection gauge, the pin grid array does not have any bent leads. The device holder also extends after the test to insure that the pin grid array is vertically elevated above the inspection gauge regardless of the test results.

    Abstract translation: 针格阵列检查装置包括具有对应于针格阵列的引线的孔的矩形矩阵的检查计。 在优选实施例中,可伸缩装置保持器延伸穿过检查计的中心开口。 器件保持器接触引脚格栅阵列的中心无引线部分,并且在对准机构抓住引脚格栅阵列之前为引脚格栅阵列提供静止位置。 位于检验仪表上方的对准机构引导引脚格栅阵列并将其对准检查仪。 装置保持架缩回,并且由于重力,销栅格阵列下降到检查量规中。 光学扫描接收器与光学扫描发射器相对安装以接收光学检测光束。 当光学扫描仪搁置在检测仪中时,光学扫描传感器将光学检测光束照射在引脚格栅阵列上。 弯曲的引线将导致与检查计量器中的相应孔的摩擦,使得引脚格栅阵列至少部分地升高到检验计上方。 如果引脚格栅阵列不平坦地放置在检验计中,并且因此至少部分地升高到检验计上方,则其阻挡光学检查光束,并且输出电路向自动操作者发信号指示引脚格栅阵列具有至少一个弯曲 铅。 如果针栅格阵列平坦地放置在检测计中,则针格栅阵列没有任何弯曲的引线。 在测试之后,器件保持器也延伸,以确保在不考虑测试结果的情况下,引脚格栅阵列垂直升高在检验计上。

    NON-VOLATILE MEMORY ENABLING SIMULTANEOUS READING AND WRITING BY TIME MULTIPLEXING A DECODE PATH
    274.
    发明申请
    NON-VOLATILE MEMORY ENABLING SIMULTANEOUS READING AND WRITING BY TIME MULTIPLEXING A DECODE PATH 审中-公开
    非易失性存储器同时启用同时读取和写入时间复制解码路径

    公开(公告)号:WO1998039773A1

    公开(公告)日:1998-09-11

    申请号:PCT/US1997014454

    申请日:1997-08-15

    CPC classification number: G11C8/08 G11C16/08 G11C16/10

    Abstract: A non-volatile memory that allows simultaneous reading and writing operations by time multiplexing a single x-decode path between read and write operations. This is accomplished using appropriate timing signals ot store/latch a first word line for a first operation and then relinquishing the x-decode path so that a second operation can load an address and access a second word line.

    Abstract translation: 一种非易失性存储器,允许通过在读取和写入操作之间对单个x-decode路径进行时间复用来同时进行读写操作。 这是使用适当的定时信号完成的,该定时信号不存储/锁存用于第一操作的第一字线,然后放弃x解码路径,使得第二操作可以加载地址并访问第二字线。

    NETWORK ADAPTER UTILIZING AN ETHERNET PROTOCOL AND UTILIZING A DIGITAL SUBSCRIBER LINE PHYSICAL LAYER DRIVER
    276.
    发明申请
    NETWORK ADAPTER UTILIZING AN ETHERNET PROTOCOL AND UTILIZING A DIGITAL SUBSCRIBER LINE PHYSICAL LAYER DRIVER 审中-公开
    网络适​​配器使用以太网协议并使用数字订户线路物理层驱动器

    公开(公告)号:WO1998020649A1

    公开(公告)日:1998-05-14

    申请号:PCT/US1997020592

    申请日:1997-11-07

    CPC classification number: H04L12/40032 H04L12/413 H04M11/062

    Abstract: An improved network adapter and architecture which combines the Ethernet bus access protocol with a digital subscriber line-based physical layer driver to provide improved performance. The use of a digital subscriber line-based physical layer driver, such as the DSL physical layer, in conjunction with the Ethernet protocol provides low cost and compatibility advantages associated with Ethernet in conjunction with the improved reliability, robustness, bandwidth, and noise resistance of the DSL layer. This allows standard Ethernet networking on noisy transmission media such as category 3 twisted pair, power lines, and other previously unusable channels.

    Abstract translation: 一种改进的网络适配器和架构,其将以太网总线访问协议与基于数字用户线的物理层驱动程序相结合,以提供改进的性能。 结合以太网协议使用基于数字用户线的物理层驱动器(例如DSL物理层)提供与以太网相关联的低成本和兼容性优点,结合改进的可靠性,鲁棒性,带宽和抗噪声性 DSL层。 这允许在有噪声的传输介质上使用标准的以太网网络,例如3类双绞线,电源线和其他以前不可用的通道。

    LOW POWER WAKE-UP SYSTEM AND METHOD
    277.
    发明申请
    LOW POWER WAKE-UP SYSTEM AND METHOD 审中-公开
    低功率唤醒系统和方法

    公开(公告)号:WO1998020609A1

    公开(公告)日:1998-05-14

    申请号:PCT/US1997020259

    申请日:1997-11-04

    CPC classification number: G06F1/3209 H03K3/0231 H03K3/03 H03K3/0322

    Abstract: An apparatus and method for providing a low power, flexible, completely digital wake-up timer. The wake-up timer is connected to a resistor and a capacitor network, thereby creating a time constant. The timer is comprised of two Schmitt-like trigger inverters, a flip-flop, and a pad driver. A wake-up pin of an associated device, for example, the handset unit of a cordless telephone, is connected to the inverters. The result from the inverters passes to a flip-flop which provides a delay. The pad driver drives a wake-up signal at the wake-up pin. A counter is included in the device to create an interrupt signal at a specific time.

    Abstract translation: 一种用于提供低功率,灵活,完全数字的唤醒定时器的装置和方法。 唤醒定时器连接到电阻和电容网络,从而产生时间常数。 定时器由两个施密特式触发反相器,触发器和焊盘驱动器组成。 相关设备的唤醒引脚连接到逆变器,例如无绳电话的手机单元。 逆变器的结果传递给提供延迟的触发器。 触发器驱动器在唤醒引脚上驱动唤醒信号。 设备中包括计数器,以在特定时间创建一个中断信号。

    A STRIDE-BASED DATA ADDRESS PREDICTION STRUCTURE
    278.
    发明申请
    A STRIDE-BASED DATA ADDRESS PREDICTION STRUCTURE 审中-公开
    基于STRIDE的数据地址预测结构

    公开(公告)号:WO1998020416A1

    公开(公告)日:1998-05-14

    申请号:PCT/US1996017516

    申请日:1996-11-04

    CPC classification number: G06F9/3455 G06F9/3832

    Abstract: A data prediction structure is provided for a superscalar microprocessor. The data prediction structure stores base addresses and stride values in a prediction array. The base address and the stride value from a location within the data prediction structure indexed by an instruction address are added to form a data prediction address which is then used to fetch data bytes into a reservation station storing an associated instruction. If the data associated with an operand address calculated by an associated functional unit resides in the reservation station, the clock cycles use to perform the load operation have occurred before the instruction reached the reservation station. Additionally, the base address is updated to the address generated by executing an instruction each time the instruction is executed, and the stride value is updated when the data prediction address is found to be incorrect.

    Abstract translation: 为超标量微处理器提供数据预测结构。 数据预测结构将基地址和步幅值存储在预测数组中。 添加由指令地址索引的数据预测结构内的位置的基地址和步幅值,以形成数据预测地址,然后将其用于将数据字节提取到存储相关指令的保留站。 如果与由关联的功能单元计算的操作数地址相关联的数据驻留在保留站中,则在指令到达保留站之前已经发生用于执行加载操作的时钟周期。 此外,基地址被更新为每次执行指令时执行指令而生成的地址,并且当发现数据预测地址不正确时更新步幅值。

    AUTOMATIC VOLUME CONTROL TO COMPENSATE FOR AMBIENT NOISE VARIATIONS
    279.
    发明申请
    AUTOMATIC VOLUME CONTROL TO COMPENSATE FOR AMBIENT NOISE VARIATIONS 审中-公开
    自动体积控制补偿环境噪声变化

    公开(公告)号:WO1998016999A1

    公开(公告)日:1998-04-23

    申请号:PCT/US1997019060

    申请日:1997-10-17

    CPC classification number: H03G3/32

    Abstract: A system and method for automatically adjusting the volume of an audio system to compensate for variations in ambient noise. The system includes a microphone for monitoring the ambient audio environment which includes output of the audio system plus environmental noise. The system also includes processing circuitry connected to the microphone. The processing circuitry varies the volume of the output of the audio system in proportion to changes in the environmental noise. The processing circuitry comprises the microphone, located to detect the ambient sound in the listening environment, an analog-to-digital converter connected to the output of the microphone, and a digital signal processor connected to the output of the analog-to-digital converter. The output signal of the DSP is an input to the volume control of the audio system.

    Abstract translation: 一种用于自动调整音频系统音量以补偿环境噪声变化的系统和方法。 该系统包括用于监视环境音频环境的麦克风,其包括音频系统的输出以及环境噪声。 该系统还包括连接到麦克风的处理电路。 处理电路根据环境噪声的变化来改变音频系统的输出音量。 所述处理电路包括所述麦克风,所述麦克风位于用于检测所述聆听环境中的环境声音,连接到所述麦克风的输出的模拟数字转换器以及连接到所述模数转换器的输出的数字信号处理器 。 DSP的输出信号是音频系统音量控制的输入。

    SYNCHRONOUS CLOCK MULTIPLEXER
    280.
    发明申请
    SYNCHRONOUS CLOCK MULTIPLEXER 审中-公开
    同步时钟多路复用器

    公开(公告)号:WO1998015888A1

    公开(公告)日:1998-04-16

    申请号:PCT/US1997010378

    申请日:1997-06-20

    CPC classification number: G06F1/08 H04J3/0688

    Abstract: A clock multiplexer including a plurality of clock selection circuits. Each clock selection circuit determines if a clock input is selected and provides the clock input to a clock output based on the determination. Each clock selection circuit futher includes deselect inputs, and a select input which is coupled to a deselect output, the deselect output providing a signal indicating if the select input is active. Each deselect input is connected to a respective one of the deselect outputs from the other clock selection circuits. In each clock selection circuit, the clock input is not provided to the clock output when one of the deselect inputs is active.

    Abstract translation: 一种包括多个时钟选择电路的时钟复用器。 每个时钟选择电路确定是否选择时钟输入,并且基于该确定将时钟输入提供给时钟输出。 每个时钟选择电路还包括取消选择输入和耦合到取消选择输出的选择输入,取消选择输出提供指示选择输入是否活动的信号。 每个取消选择输入连接到来自其它时钟选择电路的取消选择输出中的相应一个。 在每个时钟选择电路中,当其中一个取消选择输入有效时,时钟输入不提供给时钟输出。

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