Abstract:
La structure fusionnée est formée par une couche isolante (11) présentant une ouverture sur un substrat de silicium (10). Une couche façonnée de polysilicium (12) repose sur la couche isolante et est en contact avec le substrat au travers de l'ouverture; une couche de siliciure de platine (16) ayant la même forme que les couches de polysilicium-PtSi en contact avec le substrat forme une diode Schottky (40) et la région sur la couche isolante forme le fusible. Cette structure fusionnée présente des caractéristiques électriques supérieures de diode Schottky et est plus compacte que les structures de l'art antérieur.
Abstract:
Source de courant pour des régulateurs de tension utilisés dans des circuits intégrés logiques avec couplage d'émetteur (ECL) pour éliminer les variations du courant de sortie dues aux fluctuations dans la source de tension. Des transistors d'un type de polarité sont utilisés. Une source de courant (11) est connectée à un noeud de sortie (15). Un transistor (Q2) génère un courant proportionnel à la tension de sortie (15) pour développer une tension sur une résistance (12) commandant à son tour un transistor (Q3) en série avec une résistance (14) et un transistor connecté par diode (Q4). Par une action spéculaire du courant, le courant s'écoulant dans le transistor (Q4) est réfléchi (IQ1) par le transistor (Q1). Le courant de sortie (I0) est le courant s'écoulant au travers de la résistance (11) moins le courant (IQ1).
Abstract:
A pin grid array inspection device includes an inspection gauge having a rectangular matrix of holes corresponding to leads of a pin grid array. In the preferred embodiment, a retractable device holder extends through a central opening in the inspection gauge. The device holder contacts the central leadless section of the pin grid array and provides a resting place for the pin grid array before an alignment mechanism grasps the pin grid array. An alignment mechanism positioned above the inspection gauge guides the pin grid array and aligns it to the inspection gauge. The device holder retracts, and the pin grid array descends into the inspection gauge due to gravity. An optical scanning receiver is mounted opposite of an optical scanning transmitter to receive an optical inspection beam. The optical scanning transmitter shines an optical inspection beam over the pin grid array as it rests in the inspection gauge. A bent lead will cause friction with its corresponding hole in the inspection gauge causing the pin grid array to remain at least partially raised above the inspection gauge. If the pin grid array does not lie flatly in the inspection gauge, and is therefore at least partially raised above the inspection gauge, it blocks optical inspection beam, and an output circuit signals the automated operator that the pin grid array has at least one bent lead. If the pin grid array lies flatly in the inspection gauge, the pin grid array does not have any bent leads. The device holder also extends after the test to insure that the pin grid array is vertically elevated above the inspection gauge regardless of the test results.
Abstract:
A non-volatile memory that allows simultaneous reading and writing operations by time multiplexing a single x-decode path between read and write operations. This is accomplished using appropriate timing signals ot store/latch a first word line for a first operation and then relinquishing the x-decode path so that a second operation can load an address and access a second word line.
Abstract:
Undercutting (19) of conductive lines (13) in a dense array on a dielectric layer (10) containing an open field is prevented by providing one or more non-functional components (20) such as one or more non-functional conductive lines, in the dielectric layer (10) under the dense array of conductive lines (13).
Abstract:
An improved network adapter and architecture which combines the Ethernet bus access protocol with a digital subscriber line-based physical layer driver to provide improved performance. The use of a digital subscriber line-based physical layer driver, such as the DSL physical layer, in conjunction with the Ethernet protocol provides low cost and compatibility advantages associated with Ethernet in conjunction with the improved reliability, robustness, bandwidth, and noise resistance of the DSL layer. This allows standard Ethernet networking on noisy transmission media such as category 3 twisted pair, power lines, and other previously unusable channels.
Abstract:
An apparatus and method for providing a low power, flexible, completely digital wake-up timer. The wake-up timer is connected to a resistor and a capacitor network, thereby creating a time constant. The timer is comprised of two Schmitt-like trigger inverters, a flip-flop, and a pad driver. A wake-up pin of an associated device, for example, the handset unit of a cordless telephone, is connected to the inverters. The result from the inverters passes to a flip-flop which provides a delay. The pad driver drives a wake-up signal at the wake-up pin. A counter is included in the device to create an interrupt signal at a specific time.
Abstract:
A data prediction structure is provided for a superscalar microprocessor. The data prediction structure stores base addresses and stride values in a prediction array. The base address and the stride value from a location within the data prediction structure indexed by an instruction address are added to form a data prediction address which is then used to fetch data bytes into a reservation station storing an associated instruction. If the data associated with an operand address calculated by an associated functional unit resides in the reservation station, the clock cycles use to perform the load operation have occurred before the instruction reached the reservation station. Additionally, the base address is updated to the address generated by executing an instruction each time the instruction is executed, and the stride value is updated when the data prediction address is found to be incorrect.
Abstract:
A system and method for automatically adjusting the volume of an audio system to compensate for variations in ambient noise. The system includes a microphone for monitoring the ambient audio environment which includes output of the audio system plus environmental noise. The system also includes processing circuitry connected to the microphone. The processing circuitry varies the volume of the output of the audio system in proportion to changes in the environmental noise. The processing circuitry comprises the microphone, located to detect the ambient sound in the listening environment, an analog-to-digital converter connected to the output of the microphone, and a digital signal processor connected to the output of the analog-to-digital converter. The output signal of the DSP is an input to the volume control of the audio system.
Abstract:
A clock multiplexer including a plurality of clock selection circuits. Each clock selection circuit determines if a clock input is selected and provides the clock input to a clock output based on the determination. Each clock selection circuit futher includes deselect inputs, and a select input which is coupled to a deselect output, the deselect output providing a signal indicating if the select input is active. Each deselect input is connected to a respective one of the deselect outputs from the other clock selection circuits. In each clock selection circuit, the clock input is not provided to the clock output when one of the deselect inputs is active.