公开(公告)号：WO1998012839A1

公开(公告)日：1998-03-26

申请号：PCT/US1997003576

申请日：1997-03-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KALKUNTE, Mohan ,  KADAMBI, Jayant ,  MANGIN, James, Lawrence

IPC: H04L12/413

CPC classification number: H04L12/413

Abstract: A network includes a combination of carrier-sense stations and Universal Multiple Access (UMA) stations using a time slot multiple access protocol. The network is configured to include assigned time slots for the respective UMA stations and unassigned time slots reserved for the carrier-sense stations to access the shared network media. Each of the UMA stations is provided with a corresponding assigned time slot and the total number of time slots. Since the UMA stations access the media only during the assigned time slot, the carrier-sense stations can contend for access to the media after waiting a minimum interpacket gap (IPG) after sensing deassertion of the receive carrier on the media. The UMA stations may also be modified to attempt access of the media using Ethernet-compliant, carrier-sense multiple-access with collision detection (CSMA/CD) protocol when a current time slot corresponds to a mixed-use time slot.

Abstract translation: 网络包括使用时隙多址协议的载波侦听站和通用多路访问（UMA）站的组合。 网络被配置为包括用于相应UMA站的分配的时隙和为载波侦听站保留以访问共享网络媒体的未分配时隙。 每个UMA站都设有相应的分配时隙和总时隙数。 由于UMA站仅在分配的时隙期间才能访问媒体，因此在感知到媒体上的接收载波的取消消息之后等待最小分组间隙（IPG）后，载波侦听站可以争取接入媒体。 当当前时隙对应于混合使用时隙时，也可以修改UMA站以尝试使用具有冲突检测（CSMA / CD）协议的以太网兼容载波侦听多路访问的媒体访问。

公开(公告)号：WO1998008336A1

公开(公告)日：1998-02-26

申请号：PCT/US1997014479

申请日：1997-08-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  ZHOU, Yan ,  SCHOPFER, Walter, S.

IPC: H04M19/00

CPC classification number: H04M19/005

Abstract: A communication system includes a SLIC device and a SLAC device. The SLIC device and the SLAC device cooperate to control the power level provided to a subscriber line. The SLAC device includes a digital control circuit which receives a parameter signal indicative of a first parameter of the electrical power. The digital control circuit provides a digital control signal to the SLIC device in response to a sample digital control signal and the digital parameter signal. Preferably, the digital parameter signal relates to a sensed current signal and the sample digital control signal relates to a desired voltage signal. The digital control circuit can be implemented hardware or software.

Abstract translation: 通信系统包括SLIC设备和SLAC设备。 SLIC设备和SLAC设备协作来控制提供给用户线的功率电平。 SLAC设备包括数字控制电路，其接收指示电功率的第一参数的参数信号。 数字控制电路响应于采样数字控制信号和数字参数信号向SLIC设备提供数字控制信号。 优选地，数字参数信号涉及感测的电流信号，并且采样数字控制信号涉及期望的电压信号。 数字控制电路可以实现硬件或软件。

公开(公告)号：WO1998007189A1

公开(公告)日：1998-02-19

申请号：PCT/US1997009426

申请日：1997-05-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HAUSE, Fred, N. ,  MAY, Charles, E. ,  GUPTA, Sabhash

IPC: H01L21/762

CPC classification number: H01L21/76229

Abstract: An isolation technique is provided for improving the overall planarity of a fill dielectric upper surface. The fill dielectric is one used in a shallow trench process, whereby the fill dielectric is deposited within shallow trenches used in isolating active devices formed in silicon mesas. The fill dielectric is planarized by selectively removing the fill dielectric prior to chemical-mechanical polish. The fill dielectric is removed in elevationally raised regions described as those which reside essentially above the silicon mesas. A mask material is used opposite that which forms the shallow trenches. The mask material protects the shallow trenches and exposes fill dielectric directly above the silicon mesas. The fill dielectric is removed using a dry isotropic etch process to remove as much of the elevationally raised fill dielectric as possible. Once the fill dielectric is selectively removed, CMP can be more optimally performed on the remaining upper surface to achieve a surface which is substantially planar across the entire semiconductor wafer.

Abstract translation: 提供隔离技术用于改善填充电介质上表面的整体平面度。 填充电介质是在浅沟槽工艺中使用的电介质，由此填充电介质沉积在用于隔离形成在硅台面中的有源器件的浅沟槽内。 通过在化学机械抛光之前选择性地去除填充电介质来平坦化填充电介质。 在垂直升高的区域中去除填充电介质，这些区域基本上位于硅台面上方。 使用与形成浅沟槽的掩模材料相反的掩模材料。 掩模材料保护浅沟槽，并将填充电介质直接暴露在硅台面上方。 使用干各向同性蚀刻工艺去除填充电介质以尽可能多地除去高度升高的填充电介质。 一旦选择性地去除了填充电介质，就可以在剩余的上表面上更好地执行CMP，以实现在整个半导体晶片上基本平坦的表面。

公开(公告)号：WO1998007099A1

公开(公告)日：1998-02-19

申请号：PCT/US1997009545

申请日：1997-06-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  WILLIAMS, Wade, L. ,  SPILO, David, A. ,  CALVIN, Richard, T.

IPC: G06F15/78

CPC classification number: G06F15/786 ,  G06F15/7814

Abstract: A microcontroller is presented which includes a microcontroller core, an internal memory unit, an I/O pad interface unit, and several I/O pads, all formed on a single monolithic silicon substrate. The internal memory unit is configured to store data. A chip select unit within the microcontroller core generates a dedicated internal chip select (ICS#) signal which enables storage operations within the internal memory unit. Key operating parameters of the internal memory unit are stored in a single programmable internal memory chip select register (IMCSR) located within the chip select unit. The size of the internal memory unit is fixed, eliminating the need to store size information. The internal memory chip select register contains a base address field. The base address field includes a minimum number of the highest-ordered bits of a base address of the internal memory unit required to define which non-overlapping section of the physical address space the internal memory unit is mapped into. The method of accessing the internal memory unit allows backwards compatibility with existing microcontroller products. The microcontroller core also includes an execution unit and a bus interface unit. The execution unit executes microprocessor instructions, preferably instructions from an x86 instruction set. The bus interface unit handles all data transfer operations for the microcontroller core in accordance with established protocols. The I/O pad interface unit provides the microcontroller with off-chip data transfer capability, allowing the microprocessor to read data from or write data to external devices.

Abstract translation: 提出了一种微控制器，其包括单个单片硅衬底上的微控制器核心，内部存储器单元，I / O焊盘接口单元和多个I / O焊盘。 内部存储器单元被配置为存储数据。 微控制器核心内的芯片选择单元产生专用的内部芯片选择（ICS＃）信号，其使得能够在内部存储器单元内进行存储操作。 内部存储器单元的关键操作参数存储在位于芯片选择单元内的单个可编程内部存储器芯片选择寄存器（IMCSR）中。 内部存储单元的大小是固定的，无需存储大小信息。 内部存储器芯片选择寄存器包含一个基地址字段。 基地址字段包括定义内部存储器单元被映射到的物理地址空间的哪个非重叠部分所需的内部存储器单元的基地址的最低位数。 访问内部存储器单元的方法允许向后兼容现有的微控制器产品。 微控制器核心还包括执行单元和总线接口单元。 执行单元执行微处理器指令，优选来自x86指令集的指令。 总线接口单元根据已建立的协议处理单片机内核的所有数据传输操作。 I / O接口单元为微控制器提供了片外数据传输功能，允许微处理器从外部设备读取数据或向其写入数据。

公开(公告)号：WO1998007091A1

公开(公告)日：1998-02-19

申请号：PCT/US1997014298

申请日：1997-08-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HANSEN, John, P.

IPC: G06F11/00

CPC classification number: G06F11/364 ,  G06F15/7814

Abstract: A microcontroller integrates a memory accessible by the cores included thereon. Additionally the microcontroller provides an indication upon an external bus that accesses to the integrated memory are occurring. The indication provides a ready identification of internal access cycles. In one embodiment, the indication is multiplexed with a control signal upon the external bus. The microcontroller further employs a show read bus transfer, which may be optionally enabled by the user. The show read bus transfer transmits upon the external bus the read data being provided from the internal memory to a core. The cycle is presented with identical functional timing to normal read cycles. Additionally, the A/C timings of the show read bus transfer are consistent with external read transfers. Therefore, external circuitry (such as an in-circuit emulator) may capture the data from the show read bus transfer using the same circuitry used to capture external read data. The show read bus transfer may be enabled by setting a configuration register bit within the microcontroller, or by asserting a signal upon a predefined pin at the conclusion of reset of the microcontroller. By providing the predefined pin for activating the show read mode of the microcontroller, the microcontroller may be placed into show read mode for debug purposes without changing the instruction code being executed thereon.

Abstract translation: 微控制器集成了由其上包括的核可访问的存储器。 此外，微控制器在外部总线上提供对集成存储器进行访问的指示。 该指示提供了内部访问周期的准备状态。 在一个实施例中，该指示与外部总线上的控制信号多路复用。 微控制器还采用显示读总线传输，其可由用户可选地启用。 显示读取总线传输在外部总线上传送从内部存储器提供的读取数据到核心。 该周期具有与正常读取周期相同的功能定时。 此外，显示读取总线传输的A / C时序与外部读取传输一致。 因此，外部电路（如在线仿真器）可以使用与捕获外部读取数据相同的电路从显示读取总线传输中捕获数据。 可以通过在微控制器内设置配置寄存器位或者在微控制器复位结束时通过在预定义的引脚上断言信号来启用显示读总线传输。 通过提供用于激活微控制器的显示读取模式的预定义引脚，可以将微控制器置于显示读取模式以进行调试，而不改变在其上执行的指令代码。

公开(公告)号：WO1998006137A1

公开(公告)日：1998-02-12

申请号：PCT/US1997013947

申请日：1997-08-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  FULFORD, H., Jim, Jr. ,  HAUSE, Fred, N.

IPC: H01L29/78

CPC classification number: H01L29/66537 ,  H01L21/823807 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

Abstract: A selectively doped MOS transistor channel includes a deep impurity distribution and shallow impurity distribution. The deep impurity distribution is formed within high energy implant with an impurity of conductivity type opposite to the conductivity type of the source/drain regions of the transistor. In the n-channel regions, the deep impurity distribution preferably includes boron ions. The deep impurity distribution acts as a channel stop such that adjacent source/drain regions of the like type transistors are not inadvertently coupled during circuit operation. The shallow impurity distribution acts as a threshold implant by precisely controlling the doping of the transistor channel in the vicinity of the silicon oxide interface. The peak concentration of the shallow impurity distribution is located at a depth below the silicon surface which is greater than a depth typically associated with a thresold adjust implant. Because the impurity concentration of the shallow impurity distribution drops off rapidly from the peak concentration value, the concentration at the upper surface of the silicon substrate is not significantly greater than the doping of the silicon substrate itself. The light doping in the channel region of the transistor results in a substantially reduced threshold voltage for the transistor. Preferably, the threshold voltage of both the n-channel and p-channel devices has an absolute value of approximately 250 Mv. The lower threshold voltage translates into a higher IDsat when the transistor is operated under normal conditions (e.g., VGs = 3 volts, VDs = 3 volts, and VSb = 0 volts.)

Abstract translation: 选择掺杂的MOS晶体管沟道包括深杂质分布和浅杂质分布。 深度杂质分布形成在高能量注入内，杂质的导电类型与晶体管的源/漏区的导电类型相反。 在n沟道区域中，深杂质分布优选包括硼离子。 深杂质分布充当通道停止，使得相似型晶体管的相邻源极/漏极区在电路操作期间不会偶然耦合。 通过精确地控制在氧化硅界面附近的晶体管沟道的掺杂，浅杂质分布充当阈值注入。 浅杂质分布的峰值浓度位于硅表面以下的深度，其大于通常与thresold调整植入物相关的深度。 由于浅杂质分布的杂质浓度从峰值浓度值迅速下降，硅衬底上表面的浓度不会明显大于硅衬底本身的掺杂。 在晶体管的沟道区域中的轻掺杂导致晶体管的阈值电压显着降低。 优选地，n沟道和p沟道器件的阈值电压具有约250Mv的绝对值。 当晶体管在正常条件下操作时（例如，VGs = 3V，VDs = 3V，VSb = 0V），较低的阈值电压转换为较高的IDat。

公开(公告)号：WO1998002917A1

公开(公告)日：1998-01-22

申请号：PCT/US1997004991

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  WRISTERS, Derick, J. ,  FULFORD, H., Jim

IPC: H01L21/336

CPC classification number: H01L29/66659 ,  H01L21/0338 ,  H01L21/28123 ,  H01L29/7835

Abstract: The method for fabrication of a non-symmetrical IGFET of the present invention includes providing a semiconductor substrate having an insulating film and a gate material. A first portion of the gate material overlying a first region of the semiconductor substrate is removed forming a first sidewall of a gate electrode. A dopant is implanted into the first region after forming the first sidewall. After the first region is implanted, a second portion of the gate material overlying a second region of the semiconductor substrate is then removed forming a second sidewall of the gate electrode. A dopant is implanted into the second region after forming the second sidewall. Spacers are formed adjacent to each of the sidewalls of the gate electrode. Then, a dopant is implanted into portions of the first and second regions of the semiconductor substrate outside the gate electrode and the spacers. In one embodiment of the invention, the first region is a heavily doped source region and the second region is a lightly doped drain region. In another embodiment of the present invention the first region is a lightly doped drain region and the second region is a heavily doped source region. In both embodiments, a part of the lightly doped drain region is retained beneath a spacer.

Abstract translation: 本发明的非对称IGFET的制造方法包括提供具有绝缘膜和栅极材料的半导体衬底。 去除覆盖半导体衬底的第一区域的栅极材料的第一部分，形成栅电极的第一侧壁。 在形成第一侧壁之后，将掺杂剂注入第一区域。 在植入第一区域之后，然后移除覆盖半导体衬底的第二区域的栅极材料的第二部分，形成栅电极的第二侧壁。 在形成第二侧壁之后，将掺杂剂注入第二区域。 隔板与栅电极的每个侧壁相邻形成。 然后，将掺杂剂注入到半导体衬底的第一和第二区域的位于栅电极和间隔物外部的部分中。 在本发明的一个实施例中，第一区域是重掺杂的源极区域，而第二区域是轻掺杂的漏极区域。 在本发明的另一个实施例中，第一区域是轻掺杂漏极区域，第二区域是重掺杂源极区域。 在两个实施例中，轻掺杂漏极区的一部分保持在间隔物的下方。

公开(公告)号：WO1998002818A1

公开(公告)日：1998-01-22

申请号：PCT/US1996011988

申请日：1996-07-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  TRAN, Thang, M. ,  PRICKETT, James, K.

IPC: G06F12/12

CPC classification number: G06F12/126 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/382 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: A data memory unit having a load/store unit and a data cache is provided which allows store instructions that are part of a load-op-store instruction to be executed with one access to a data cache. The load/store unit is configured with a load/store buffer having a checked bit and a way field for each buffer storage location. For load-op-store instructions, the checked bit associated with the store portion of the instruction is set when the load portion of the instruction accesses and hits the data cache. Also, the way field associated with the store portion is set to the way of the data cache in which the load portion hits. The data cache is configured with a locking mechanism for each cache line stored in the data cache. When the load portion of a load-op-store instruction is executed, the associated line is locked such that the line will remain in the data cache until a store instruction executes. In this way, the store portion of the load-op-store instruction is guaranteed to hit the data cache. The store may then store its data into the data cache without first performing a read cycle to determine if the store address hits the data cache.

Abstract translation: 提供具有加载/存储单元和数据高速缓存的数据存储单元，其允许作为加载操作存储指令的一部分的存储指令通过对数据高速缓存的一次访问来执行。 加载/存储单元配置有具有每个缓冲存储位置的检查位和方式字段的加载/存储缓冲器。 对于加载操作存储指令，当指令的加载部分访问并且命中数据高速缓存时，设置与指令的存储部分相关联的检查位。 此外，与存储部分相关联的方式字段被设置为加载部分命中的数据高速缓存的方式。 数据高速缓存配置有存储在数据高速缓存中的每个高速缓存行的锁定机制。 当执行加载操作存储指令的加载部分时，相关联的行被锁定，使得行将保留在数据高速缓存中直到存储指令执行。 以这种方式，加载操作存储指令的存储部分被保证命中数据高速缓存。 然后，存储器可以将其数据存储到数据高速缓存中，而不首先执行读取周期以确定存储地址是否触发数据高速缓存。

公开(公告)号：WO1998002800A1

公开(公告)日：1998-01-22

申请号：PCT/US1996011756

申请日：1996-07-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  TRAN, Thang, M. ,  WITT, David, B.

IPC: G06F09/38

CPC classification number: G06F9/3844

Abstract: An update unit for an array in an integrated circuit is provided. The update unit delays the update of the array until a clock cycle in which the functional input to the array is idle. The input port normally used by the functional input is then used to perform the update. During clock cycles between receiving the update and storing the update into the array, the update unit compares the current functional input address to the update address. If the current functional input address matches the update address, then the update value is provided as the output of the array. Otherwise, the information stored in the indexed storage location is provided. In this manner, the update appears to have been performed in the clock cycle that the update value was received, as in a dual-ported array. A particular embodiment of the update unit is a branch prediction array update unit. This unit is described in detail.

Abstract translation: 提供集成电路中的阵列的更新单元。 更新单元延迟阵列的更新，直到阵列的功能输入空闲的时钟周期为止。 通常由功能输入端使用的输入端口用于执行更新。 在接收到更新并将更新存储到阵列中的时钟周期期间，更新单元将当前功能输入地址与更新地址进行比较。 如果当前功能输入地址与更新地址匹配，则更新值作为数组的输出提供。 否则，提供存储在索引存储位置中的信息。 以这种方式，更新似乎是在接收到更新值的时钟周期中执行的，如双端口阵列中那样。 更新单元的特定实施例是分支预测阵列更新单元。 详细描述了该单元。

公开(公告)号：WO1998002796A1

公开(公告)日：1998-01-22

申请号：PCT/US1997012151

申请日：1997-07-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  STILES, David

IPC: G06F07/50

CPC classification number: G06F7/485 ,  G06F7/483 ,  G06F7/49915 ,  G06F7/49936 ,  G06F7/49947 ,  G06F2207/3884

Abstract: A numeric processor system is provided with a floating point adder subsystem having a set of parallel dedicated numeric processors, each of the numeric processors comprising a plurality of calculation units operative in parallel on common operands to present candidate results, at least one of each of the dedicated numeric processors producing a correct result, the dedicated numeric processors reporting status information to a control unit, wherein the control unit determines which of the candidate results is the correct result for further processing. The numeric processor system according to the invention is capable of producing a final result on a floating point computation with very low latency, that is, with very few gate delays for a complete and independent computation. The numeric processor system according to the invention is particularly useful in a computation environment where successive floating point calculations are dependent. The invention is based on decomposing a normally serial algorithm into an extensive set of parallel candidate operations on different fragments of the operands, the operations being based on time-shortening assumptions, and then choosing the correct result after the operations rather than affecting the operands and modifying the calculation in series along a critical path as status information first becomes available.

Abstract translation: 数字处理器系统具有一个具有一组并行专用数字处理器的浮点加法器子系统，每个数字处理器包括多个计算单元并行地运行在共同的操作数上以呈现候选结果，每一个 产生正确结果的专用数字处理器，专用数字处理器向控制单元报告状态信息，其中控制单元确定哪个候选结果是正确的结果用于进一步处理。 根据本发明的数字处理器系统能够以非常低的等待时间在浮点计算上产生最终结果，即，对于完全和独立的计算，具有非常少的门延迟。 根据本发明的数字处理器系统在依赖于连续浮点计算的计算环境中特别有用。 本发明基于将正常串行算法分解成对操作数的不同片段的大量并行候选操作，操作基于时间缩短假设，然后在操作之后选择正确的结果，而不是影响操作数，并且 当状态信息首先变为可用时，沿着关键路径串联修改计算。