公开(公告)号：EP0609264A1

公开(公告)日：1994-08-10

申请号：EP92920784.0

申请日：1992-09-23

Applicant: APTIX CORPORATION

Inventor： MOHSEN, Amr, M.

IPC: H01L23 ,  H03K17

CPC classification number: H03K17/002 ,  H01L23/525 ,  H01L2924/0002 ,  H03K17/693 ,  H01L2924/00

Abstract: Zone matricielle d'interconnexion universelle (605) comportant un premier ensemble de conducteurs (608-1 à 608-J) formés dans un premier sens, un second ensemble de conducteurs (609-1 à 609-K) formés dans un second sens non parallèle au premier, et une structure destinée à interconnecter électriquement certains conducteurs sélectionnés dans le premier ensemble de conducteurs (608-1 à 608-J), et un ou plusieurs conducteurs compris dans le second ensemble de conducteurs (609-1 à 609-K). Des plages de connexion (607-1,1 à 607-M,N) sont raccordées à certains conducteurs sélectionnés dans le premier ensemble de conducteurs (608-1 à 608-J) et dans le second ensemble de conducteurs (609-1 à 609-K). Certains conducteurs sélectionnés sont segmentés de manière à permettre à l'une quelconque des plages de connexion de se raccorder à une ou plusieurs autre(s) plage(s) de connexion (607-1,1 à 607-M,N) sans mettre hors fonction les plages de connexion (607-1,1 à 607-M,N) non destinées à être raccordées de cette façon.

公开(公告)号：EP0592111A2

公开(公告)日：1994-04-13

申请号：EP93307118.5

申请日：1993-09-09

Applicant: APTIX CORPORATION

Inventor： Mohsen, Amr

IPC: H01L23/522 ,  H01L25/04 ,  H01L23/538 ,  H01L25/065 ,  H01L27/118 ,  H03K19/177

CPC classification number: H01L27/11898 ,  H01L23/525 ,  H01L23/5382 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03K19/17704 ,  H01L2924/00

Abstract: A high I/O count integrated circuit is disposed on a semiconductor chip having opposing faces and comprises a plurality of functional circuit modules, each having inputs and at least one output having a first drive capability. A plurality of a first type of I/O nodes, each comprising a first conductive structure is disposed in a first I/O node array on the surface of a first one of the semiconductor chip faces. A plurality of a second type of I/O nodes, each comprising a first conductive structure is disposed on the first semiconductor chip face. An interconnect architecture comprising a plurality of conductors is superimposed on the functional circuit modules, the interconnect architecture comprises a plurality of interconnect conductors. Selected ones of the interconnect conductors are connectable to the inputs and at least one output of selected ones of the functional circuit modules by electrically programmable user-programmable interconnect elements. Selected ones of the interconnect conductors are connectable to other selected ones of the interconnect conductors by user-programmable interconnect elements. Selected ones of the interconnect conductors are connectable to the first I/O nodes by electrically programmable user-programmable interconnect elements. Selected ones of the interconnect conductors are connectable to the second I/O nodes by electrically programmable user-programmable interconnect elements.

Abstract translation: 高I ​​/ O计数集成电路设置在具有相对面的半导体芯片上，并且包括多个功能电路模块，每个功能电路模块具有输入和具有第一驱动能力的至少一个输出。 在第一个半导体芯片面的表面上的第一I / O节点阵列中设置多个第一类型的I / O节点，每个节点包括第一导电结构。 在第一半导体芯片面上设置多个第二类型的I / O节点，每个I / O节点包括第一导电结构。 包括多个导体的互连体系结构叠加在功能电路模块上，互连体系结构包括多个互连导体。 通过电可编程用户可编程互连元件，所选择的互连导体中的所选择的一些功能电路模块能够连接至输入和所选功能电路模块的至少一个输出。 通过用户可编程互连元件，选定的互连导体中的其中选定的互连导体是可连接的。 通过电可编程用户可编程互连元件，选定的一些互连导体可连接到第一I / O节点。 通过电可编程用户可编程互连元件，选定的一些互连导体可连接到第二I / O节点。

公开(公告)号：EP0575186A2

公开(公告)日：1993-12-22

申请号：EP93304756.5

申请日：1993-06-17

Applicant: APTIX CORPORATION

Inventor： Guo, Ta-Pen ,  Srinivasan, Adi

IPC: H03K19/017 ,  G11C11/419 ,  G11C8/00

CPC classification number: H03K19/01721

Abstract: A pullup circuit for use with plurality of N-Channel pulldown transistors (14a,..., 14n) connected to a bit line (12) includes a P-channel MOS pullup transistor (10) connected between the bit line (12) and a voltage rail (V DD ). An inverter (32) is connected between the bit line (12) and the drain of an N-Channel MOS transistor (34) having its gate connected to the voltage rail (V DD ) and its source connected to the gate of the P-Channel MOS pullup transistor (10). A first P-Channel MOS transistor (36) is connected between the voltage rail (V DD ) and the gate of the P-Channel MOS pullup transistor (10). A second P-Channel MOS transistor (38) having its gate connected to ground is connected between the bit line (12) and the gate of the first P-Channel MOS transistor (10). Four P-Channel MOS divider transistors (40,42,44,46) are connected between the drain of the first P-Channel MOS transistor (10) and ground. The gates of the P-Channel MOS divider transistors (40,42,44,46) are connected together to ground. The P-Channel MOS pullup transistor (10) and the N-Channel MOS pulldown transistors (14a,...,14n) are large. The first and second P-Channel MOS transistors (36,38), the first N-Channel MOS transistor (34), and the P-Channel MOS divider transistors (40,42,44,46) are close to minimum size. The P-Channel and N-Channel devices comprising the inverter devices are larger than minimum size.

Abstract translation: 连接到位线的多个N沟道下拉晶体管使用的上拉电路包括连接在位线和电压轨之间的P沟道MOS上拉晶体管。 逆变器连接在N沟道MOS晶体管的位线和漏极之间，其栅极连接到电压轨，其源极连接到P沟道MOS上拉晶体管的栅极。 第一P沟道MOS晶体管连接在电压轨和P沟道MOS上拉晶体管的栅极之间。 其栅极连接到地的第二P沟道MOS晶体管连接在位线和第一P沟道MOS晶体管的栅极之间。 四个P沟道MOS分压器晶体管连接在第一P沟道MOS晶体管的漏极和地之间。 P沟道MOS分压器晶体管的栅极连接在一起。 P沟道MOS上拉晶体管和N沟道MOS下拉晶体管很大。 第一和第二P沟道MOS晶体管，第一N沟道MOS晶体管和P沟道MOS分压器晶体管接近于最小尺寸。 包括逆变器装置的P沟道和N沟道器件大于最小尺寸。

公开(公告)号：EP0518701A2

公开(公告)日：1992-12-16

申请号：EP92305443.1

申请日：1992-06-12

Applicant: APTIX CORPORATION

Inventor： Osann, Robert, Jr. ,  Shaw, George A., Jr. ,  Mohsen, Amr M.

IPC: G06F15/60 ,  H05K1/00

CPC classification number: H01L23/5382 ,  H01L2224/49171 ,  H01L2924/10253 ,  H05K1/0289 ,  H05K1/112 ,  H05K2201/09945 ,  H05K2201/10689 ,  H05K2203/175 ,  H01L2924/00

Abstract: The invention uses a programmable interconnect substrate having a plurality of conductive and interconnectable vias located on one or both surfaces thereof. A customised pattern of bonding pads is then formed over the one or both surface of the substrate which correspond to the terminal footprints of specific surface mounted packages intended to be mounted on the substrate. A generalised pattern of bonding pads may also be formed on the surface of the substrate for electrically connecting terminals of bare dice thereto by means of thin wire. All bonding pads are electrically connected to one or more vias by direct electrical contact or by a conductive trace extending from the bonding pad to a nearly via.

Abstract translation: 本发明使用具有位于其一个或两个表面上的多个导电和可互连通孔的可编程互连基板。 然后在衬底的一个或两个表面上形成定制的焊盘图案，该表面对应于期望安装在衬底上的特定表面安装封装的端子脚印。 也可以在基板的表面上形成接合焊盘的一般化图案，用于通过细线电连接裸芯片的端子。 所有接合焊盘通过直接电接触或通过从接合焊盘延伸到几乎通孔的导电迹线而电连接到一个或多个通孔。

公开(公告)号：EP0481703A3

公开(公告)日：1992-08-05

申请号：EP91309424.9

申请日：1991-10-14

Applicant: APTIX CORPORATION

Inventor： Mohsen, Amr M.

IPC: G06F15/60 ,  H01L23/538

CPC classification number: H01L22/22 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/318505 ,  G01R31/318538 ,  G11C29/30 ,  H01L23/5252 ,  H01L23/528 ,  H01L23/5382 ,  H01L2924/0002 ,  H05K1/0286 ,  H01L2924/00

Abstract: An interconnect substrate has formed thereon a first plurality of conductive leads (108-1...108-J) and a second plurality of conductive leads (109-1...109-K). A plurality of cells (106-1,1...106-J,K) are formed in the substrate, each cell having a number of bonding pads (107-1...107-M) formed on the surface of the substrate above the region of the substrate in which the cell is formed, thereby to allow a plurality of integrated circuit chips and electrical components to be attached to the substrate and electrically connected to the cells. Devices and programming elements in the substrate or in integrated circuits mounted on the substrate allow selected connections to be formed between selected ones of the conductive leads to be connected electrically thereby to allow selected components mounted on the substrate to be electrically interconnected. Other devices in the substrate or in integrated circuits mounted on the substrate allow testing of the components mounted on the substrate to determine their performance and the checking of the integrity of the connections formed between conductive leads.

公开(公告)号：EP0481703A2

公开(公告)日：1992-04-22

申请号：EP91309424.9

申请日：1991-10-14

Applicant: APTIX CORPORATION

Inventor： Mohsen, Amr M.

IPC: G06F15/60 ,  H01L23/538

CPC classification number: H01L22/22 ,  G01R31/2853 ,  G01R31/2884 ,  G01R31/318505 ,  G01R31/318538 ,  G11C29/30 ,  H01L23/5252 ,  H01L23/528 ,  H01L23/5382 ,  H01L2924/0002 ,  H05K1/0286 ,  H01L2924/00

Abstract: An interconnect substrate has formed thereon a first plurality of conductive leads (108-1...108-J) and a second plurality of conductive leads (109-1...109-K). A plurality of cells (106-1,1...106-J,K) are formed in the substrate, each cell having a number of bonding pads (107-1...107-M) formed on the surface of the substrate above the region of the substrate in which the cell is formed, thereby to allow a plurality of integrated circuit chips and electrical components to be attached to the substrate and electrically connected to the cells. Devices and programming elements in the substrate or in integrated circuits mounted on the substrate allow selected connections to be formed between selected ones of the conductive leads to be connected electrically thereby to allow selected components mounted on the substrate to be electrically interconnected.
Other devices in the substrate or in integrated circuits mounted on the substrate allow testing of the components mounted on the substrate to determine their performance and the checking of the integrity of the connections formed between conductive leads.

Abstract translation: 互连基板上形成有第一多个导电引线（108-1 ... 108-J）和第二多个导电引线（109-1 ... 109-K）。 多个单元（106-1,1 ... 106-J，K）形成在基板中，每个单元具有形成在该表面上的多个接合焊盘（107-1 ... 107-M） 在其上形成单元的基板的区域上方，从而允许多个集成电路芯片和电气部件附接到基板并电连接到单元。 衬底中的装置和编程元件或安装在衬底上的集成电路允许在电连接的导电引线的选定导体之间形成所选择的连接，从而允许安装在衬底上的选定部件电连接。 衬底中的其他器件或安装在衬底上的集成电路中的器件允许测试安装在衬底上的部件，以确定其性能以及检查导电引线之间形成的连接的完整性。