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    NETWORK-BASED CIRCUIT PROTOTYPING USING A SECURE SERVER
    2.
    发明申请
    NETWORK-BASED CIRCUIT PROTOTYPING USING A SECURE SERVER 审中-公开

    公开(公告)号：WO2001093001A3

    公开(公告)日：2001-12-06

    申请号：PCT/US2001/017232

    申请日：2001-05-25

    Applicant: APTIX CORPORATION

    Inventor： MOHSEN, Amr, M. ,  BICZEK, Robert ,  HUANG, Thomas, B. ,  ROSQVIST, Leif ,  SIU, Francis ,  UNDERSETH, Mitchell

    IPC: G06F17/50

    Abstract: A method and system are provided for prototyping a circuit design using a secure server connected to a network. A customer's client computer transfers an encrypted circuit design to a secure server. An consulting engineer's client computer then connects to the server, accesses the design, and prototypes the design. The prototype is sent to the customer, either as programming files which the customer uses to program a hardware prototype, as a programmed hardware prototype, or as programming files stored in flash memory which the customer uses to program a configurable hardware prototype. In one embodiment, the server is connected to the public network through a firewall and the circuit design file is encrypted. The customer's client computer transfers the circuit design to the server using a password to create through the firewall a virtual public network authorized by the server.

    UNIVERSAL INTERCONNECT MATRIX ARRAY
    3.
    发明申请
    UNIVERSAL INTERCONNECT MATRIX ARRAY 审中-公开
    通用互连矩阵阵列

    公开(公告)号：WO1993006559A1

    公开(公告)日：1993-04-01

    申请号：PCT/US1992008115

    申请日：1992-09-23

    Applicant: APTIX CORPORATION

    Inventor： APTIX CORPORATION ,  MOHSEN, Amr, M.

    IPC: G06F15/60

    CPC classification number: H03K17/002 ,  H01L23/525 ,  H01L2924/0002 ,  H03K17/693 ,  H01L2924/00

    Abstract: A universal interconnect matrix area array (605) comprised of a first set of conductive leads (608-1 through 608-J) formed in a first direction, a second set of conductive leads (609-1 through 609-K) formed in a second direction, the second direction being not parallel to the first direction, and structure for electrically interconnecting selected ones of the conductive leads in the first set of conductive leads (608-1 through 608-J) to one or more of the conductive leads in the second set of conductive leads (609-1 through 609-K). Input/output pads (607-1,1 through 607-M,N) are formed and connected to selected ones of the first set of conductive leads (608-1 through 608-J) and second set of conductive leads (609-1 through 609-K). Selected ones of the conductive leads are segmented thereby to allow any input/output pad to be connected to one or more of the other input/output pads (607-1,1 through 607-M,N) without removing from use any input/output pads (607-1,1 through 607-M,N), not intended to be so connected.

    Abstract translation: 由在第一方向上形成的第一组导电引线（608-1至608-J），第二组导电引线（609-1至609-K）形成的通用互连矩阵区阵列（605） 第二方向，第二方向不平行于第一方向，以及用于将第一组导电引线（608-1至608-J）中的导电引线中的一些导电引线与一个或多个导电引线电连接的结构 第二组导电引线（609-1至609-K）。 形成输入/输出焊盘（607-1,1至607-M，N）并将其连接到第一组导电引线（608-1至608-J）和第二组导电引线（609-1 通过609-K）。 所选择的导电引线被分段，从而允许任何输入/输出焊盘连接到一个或多个其它输入/输出焊盘（607-1,1到607-M，N），而不用使用任何输入/ 输出焊盘（607-1,1至607-M，N），不打算如此连接。

    PROGRAMMABLE INTERCONNECT ARCHITECTURE
    4.
    发明申请
    PROGRAMMABLE INTERCONNECT ARCHITECTURE 审中-公开
    可编程互连架构

    公开(公告)号：WO1994015399A1

    公开(公告)日：1994-07-07

    申请号：PCT/US1993012119

    申请日：1993-12-16

    Applicant: APTIX CORPORATION

    Inventor： APTIX CORPORATION ,  VERHEYEN, Henry, T. ,  KRING, Charles J., Jr. ,  OSANN, Robert, Jr.

    IPC: H03K17/693

    CPC classification number: H03K19/17704 ,  H05K1/0286 ,  H05K1/18

    Abstract: A programmable interconnect system includes a two-level hierarchical structure of programmable interconnect chips (120.1-120.6 and 130.1-130.2) on a circuit board (110). The first-level, or "local", interconnect chips are connected to user components (150.1-150.5). A plurality of second-level, or "global", interconnect chips interconnect the local interconnect chips so that every local chip is connected to every global chip. Such a system allows connecting any pin of any user component to any other pin of any user component by a conductive path passing through at most three interconnect chips. A large number of such paths are provided even in embodiments with a large number of interconnect chips.

    Abstract translation: 可编程互连系统包括在电路板（110）上的可编程互连芯片（120.1-120.6和130.1-130.2）的两级分层结构。 第一级或“本地”互连芯片连接到用户组件（150.1-150.5）。 多个二级或“全局”互连芯片互连局部互连芯片，使得每个本地芯片连接到每个全局芯片。 这种系统允许通过最多三个互连芯片的导电路径将任何用户组件的任何引脚连接到任何用户组件的任何其他引脚。 即使在具有大量互连芯片的实施例中，也提供了大量这样的路径。

    Field programmable printed circuit board
    5.
    发明申请
    Field programmable printed circuit board 审中-公开
    现场可编程印刷电路板

    公开(公告)号：US20020100010A1

    公开(公告)日：2002-07-25

    申请号：US10052671

    申请日：2002-01-17

    Applicant: Aptix Corporation

    Inventor： Amr M. Mohsen

    IPC: G06F017/50

    CPC classification number: G06F17/5027 ,  G01R31/2818 ,  G06F17/5068 ,  H01L23/525 ,  H01L2924/0002 ,  H05K1/029 ,  H05K1/0298 ,  H05K3/222 ,  H05K3/429 ,  H05K2201/10212 ,  H05K2201/10689 ,  H01L2924/00

    Abstract: A field programmable printed circuit board is provided which includes a multiplicity of component contacts for making electrical contact to the leads of electronic components to be mounted on the printed circuit board, a corresponding multiplicity of interconnect contacts for receipt of the leads on the package or packages of a programmable integrated circuit or circuits for interconnecting as desired the electronic components, and one or more layers of conductive traces formed on the printed circuit board, each conductive trace uniquely connecting electrically one component contact to one interconnect contact.

    Abstract translation: 提供了现场可编程印刷电路板，其包括多个组件触点，用于与要安装在印刷电路板上的电子部件的引线电接触;相应的多个互连触点，用于接收封装或封装上的引线 可编程集成电路或用于根据需要互连电子部件的电路，以及形成在印刷电路板上的一层或多层导电迹线，每个导电迹线将电气单一元件触点唯一地连接到​​一个互连触点。

    Field programmable circuit module
    7.
    发明公开
    Field programmable circuit module 失效
    现场可编程电路模块

    公开(公告)号：EP0518701A3

    公开(公告)日：1993-04-21

    申请号：EP92305443.1

    申请日：1992-06-12

    Applicant: APTIX CORPORATION

    Inventor： Osann, Robert, Jr. ,  Shaw, George A., Jr. ,  Mohsen, Amr M.

    IPC: G06F15/60 ,  H05K1/00

    CPC classification number: H01L23/5382 ,  H01L2224/49171 ,  H01L2924/10253 ,  H05K1/0289 ,  H05K1/112 ,  H05K2201/09945 ,  H05K2201/10689 ,  H05K2203/175 ,  H01L2924/00

    Abstract: The invention uses a programmable interconnect substrate having a plurality of conductive and interconnectable vias located on one or both surfaces thereof. A customised pattern of bonding pads is then formed over the one or both surface of the substrate which correspond to the terminal footprints of specific surface mounted packages intended to be mounted on the substrate. A generalised pattern of bonding pads may also be formed on the surface of the substrate for electrically connecting terminals of bare dice thereto by means of thin wire. All bonding pads are electrically connected to one or more vias by direct electrical contact or by a conductive trace extending from the bonding pad to a nearly via.

    Abstract translation: 本发明使用具有位于其一个或两个表面上的多个导电和可互连通孔的可编程互连基板。 然后在衬底的一个或两个表面上形成定制的焊盘图案，该表面对应于期望安装在衬底上的特定表面安装封装的端子脚印。 也可以在基板的表面上形成接合焊盘的一般化图案，用于通过细线电连接裸芯片的端子。 所有接合焊盘通过直接电接触或通过从接合焊盘延伸到几乎通孔的导电迹线而电连接到一个或多个通孔。

    Low current, fast, CMOS static pullup circuit for static random-access memories
    8.
    发明公开
    Low current, fast, CMOS static pullup circuit for static random-access memories 失效
    用于静态随机存取存储器的低电流，快速CMOS静态抽头电路

    公开(公告)号：EP0575186A3

    公开(公告)日：1994-06-22

    申请号：EP93304756.5

    申请日：1993-06-17

    Applicant: APTIX CORPORATION

    Inventor： Guo, Ta-Pen ,  Srinivasan, Adi

    IPC: H03K19/017 ,  G11C11/419 ,  G11C8/00

    CPC classification number: H03K19/01721

    Abstract: A pullup circuit for use with plurality of N-Channel pulldown transistors (14a,..., 14n) connected to a bit line (12) includes a P-channel MOS pullup transistor (10) connected between the bit line (12) and a voltage rail (V DD ). An inverter (32) is connected between the bit line (12) and the drain of an N-Channel MOS transistor (34) having its gate connected to the voltage rail (V DD ) and its source connected to the gate of the P-Channel MOS pullup transistor (10). A first P-Channel MOS transistor (36) is connected between the voltage rail (V DD ) and the gate of the P-Channel MOS pullup transistor (10). A second P-Channel MOS transistor (38) having its gate connected to ground is connected between the bit line (12) and the gate of the first P-Channel MOS transistor (10). Four P-Channel MOS divider transistors (40,42,44,46) are connected between the drain of the first P-Channel MOS transistor (10) and ground. The gates of the P-Channel MOS divider transistors (40,42,44,46) are connected together to ground. The P-Channel MOS pullup transistor (10) and the N-Channel MOS pulldown transistors (14a,...,14n) are large. The first and second P-Channel MOS transistors (36,38), the first N-Channel MOS transistor (34), and the P-Channel MOS divider transistors (40,42,44,46) are close to minimum size. The P-Channel and N-Channel devices comprising the inverter devices are larger than minimum size.

    Memory cell with known state on power-up
    10.
    发明公开
    Memory cell with known state on power-up 失效
    与功率后一个已知的状态的存储器单元被接通。

    公开(公告)号：EP0581443A2

    公开(公告)日：1994-02-02

    申请号：EP93305068.4

    申请日：1993-06-29

    Applicant: APTIX CORPORATION

    Inventor： Guo, Ta-Pen ,  Srinivasan, Adi

    IPC: G11C7/00

    CPC classification number: G11C7/20

    Abstract: Apparatus for forcing a memory cell to a known state upon power-up includes circuitry for providing two signals PWRUP and PWRUPB which are used during chip power-up. At power-up, as V cc rises from 0 volt to 3.5 volts, the PWRUP signal follows V cc and the PWRUPB signal maintains 0 volts. The PWRUP and PWRUPB signals are used to drive the gates of P-Channel and N-Channel MOS transistors, respectively, including pass gates connected between word line driver circuits and bit line driver circuits driving the word lines and bit lines associated with the memory cells. In addition, the PWRUPB signal is used to drive P-Channel MOS pullup transistors connected between the word lines and V cc and the bit lines and V cc . During power-up, the pass gates are disabled, disconnecting the word lines and bit lines from their drivers. The word lines and bit lines are forced to follow the rise of V cc by the P-Channel pullup transistors. When V cc reaches its desired value, the PWRUP signal goes to 0 volts and the PWRUPB signal goes to V cc , thus turning on the pass gates to connect the word line and bit line driver circuits to the word lines and bit lines. The V cc final PWRUPB signal turns off the P-Channel MOS pullup transistors connected between the word lines and V cc and the bit lines and Vcc.

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