公开(公告)号：US20180294218A1

公开(公告)日：2018-10-11

申请号：US15657208

申请日：2017-07-24

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu ,  Wei-Jen Lai

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49861 ,  H01L23/4952 ,  H01L23/49531 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48227 ,  H01L2224/48235

Abstract: A package structure includes a lead frame, an insulator, a plurality of conductive vias, a patterned metal layer, and a chip. The lead frame includes a plurality of contacts. The insulator covers the lead frame. The conductive vias are disposed on the insulator and connected to the contacts. The patterned metal layer covers an outer surface of the insulator and includes a groove and a circuit portion. The circuit portion is connected to and covers the conductive vias and contacts. The groove surrounds the circuit portion such that the circuit portion is electrically insulated from the rest of the patterned metal layer. A surface of the insulator exposed by the groove is lower than the outer surface. The chip is disposed on the insulator and electrically connected to the circuit portion.

公开(公告)号：US20170256479A1

公开(公告)日：2017-09-07

申请号：US15600793

申请日：2017-05-22

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu ,  Wei-Jen Lai

IPC: H01L23/495 ,  H01L23/60

CPC classification number: H01L23/49503 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/053 ,  H01L23/481 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49558 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/60 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/186 ,  H01L2924/19105 ,  H05K1/0373 ,  H05K1/113 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674

Abstract: A package structure including a substrate, a first lead frame, a first metal layer, at least one chip, a base and a second metal layer is provided. The base includes a plurality of openings. The first lead frame is embedded in the substrate and includes a plurality of first pads, where the openings expose the first pads. The first metal layer covers the exposed first pads. The chip is disposed on the substrate and electrically connected to the first metal layer and the first pads. The base covers the substrate with its bonding surface. The second metal layer covers a base surface of the base.

公开(公告)号：US20160233152A1

公开(公告)日：2016-08-11

申请号：US15133244

申请日：2016-04-20

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu

IPC: H01L23/495 ,  H01L21/768

CPC classification number: H01L23/49586 ,  H01L21/4828 ,  H01L21/76823 ,  H01L21/76825 ,  H01L23/13 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49558 ,  H01L23/49861 ,  H01L2224/48091 ,  H01L2924/181 ,  H05K1/0373 ,  H05K1/113 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A package structure includes a lead frame, a selective-electroplating epoxy compound, conductive vias and a patterned circuit layer. The lead frame includes a metal stud array having metal studs. The selective-electroplating epoxy compound covers the metal stud array. The selective-electroplating epoxy compound includes non-conductive metal complex. The conductive vias are directly embedded in the selective electroplating epoxy compound to be respectively connected to the metal studs and extended to a top surface of the selective-electroplating epoxy compound. Each of the conductive vias includes a lower segment connected to the corresponding metal stud and an upper segment connected to the lower segment and extended to the top surface, and a smallest diameter of the upper segment is greater than a largest diameter of the lower segment. The patterned circuit layer is directly disposed on the top surface and electrically connected to the conductive vias.

Abstract translation: 封装结构包括引线框，选择性电镀环氧化合物，导电通孔和图案化电路层。 引线框架包括具有金属螺柱的金属螺柱阵列。 选择性电镀环氧化合物覆盖金属螺柱阵列。 选择性电镀环氧化合物包括非导电金属络合物。 导电通孔直接嵌入选择性电镀环氧化合物中，以分别连接到金属螺柱并延伸到选择性电镀环氧化合物的顶表面。 每个导电通孔包括连接到相应的金属螺柱的下部段和连接到下部段并延伸到顶部表面的上段，并且上段的最小直径大于下段的最大直径。 图案化电路层直接设置在顶表面上并电连接到导电通孔。

公开(公告)号：US20150373849A1

公开(公告)日：2015-12-24

申请号：US14663447

申请日：2015-03-19

Applicant: IBIS Innotech Inc.

Inventor： Chih-Kung Huang ,  Wei-Jen Lai ,  Wen-Chun Liu

IPC: H05K1/11 ,  H05K1/18 ,  H05K1/03

CPC classification number: H05K1/0373 ,  H01L21/568 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L25/04 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/96 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195 ,  H01L2924/1715 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19105 ,  H05K1/113 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014

Abstract: A package structure includes a selective-electroplating epoxy compound, a first patterned circuit layer, second patterned circuit layers, metal studs, contact pads and conductive vias. The selective-electroplating epoxy compound includes cavities, a first surface and a second surface. The cavities disposed on the first surface in array arrangement. The selective-electroplating epoxy compound is formed by combining non-conductive metal complex. The metal studs are disposed in the cavities respectively and protruded from the first surface. The first patterned circuit layer is directly disposed on the first surface. The selective-electroplating epoxy compound exposes a top surface of the patterned circuit layer. The top surface is lower than or coplanar with the first surface. The second patterned circuit layers are directly disposed on the second surface. The conductive vias are disposed at the selective-electroplating epoxy compound to electrically connect the second patterned circuit layers to the corresponding metal studs.

Abstract translation: 封装结构包括选择性电镀环氧化合物，第一图案化电路层，第二图案化电路层，金属柱，接触焊盘和导电通孔。 选择性电镀环氧化合物包括空腔，第一表面和第二表面。 排列在第一表面上的空腔。 选择性电镀环氧化合物通过组合非导电金属络合物形成。 金属螺柱分别设置在空腔中并从第一表面突出。 第一图案化电路层直接设置在第一表面上。 选择性电镀环氧化合物暴露图案化电路层的顶表面。 顶面低于或与第一表面共面。 第二图案化电路层直接设置在第二表面上。 导电通孔设置在选择性电镀环氧化合物处，以将第二图案化电路层电连接到相应的金属螺柱。

公开(公告)号：US20150061814A1

公开(公告)日：2015-03-05

申请号：US14475950

申请日：2014-09-03

Applicant: IBIS INNOTECH INC.

Inventor： Wei-Jen LAI ,  Chih-Kung HUANG

IPC: H01F27/28

CPC classification number: H05K1/0306 ,  H01F27/2804 ,  H01L23/15 ,  H01L23/49838 ,  H01L33/486 ,  H01L33/62 ,  H01L2924/0002 ,  H05K2201/0175 ,  H01L2924/00

Abstract: A ferrite circuit board includes a substrate and a wire. The substrate is made of ferrite and provided with a surface and an elongated groove recessed from the surface. The elongated groove has an inner wall having a roughness Ra ranging from 0.1 μm to 20 μm. The wire is embedded in the elongated groove of the substrate, such that the wire is not easily separated from the substrate. The ferrite circuit board can be used as an inductor to provide abundant functionality.

Abstract translation: 铁氧体电路板包括基板和导线。 基板由铁氧体制成，并具有从表面凹陷的表面和细长槽。 细长槽具有表面粗糙度Ra为0.1μm〜20μm的内壁。 导线被嵌入基板的细长槽中，使得导线不容易与基板分离。 铁氧体电路板可用作电感器以提供丰富的功能。

公开(公告)号：US10256180B2

公开(公告)日：2019-04-09

申请号：US15461499

申请日：2017-03-17

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu ,  Wei-Jen Lai

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/29 ,  H01L23/48 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/18 ,  H05K3/40 ,  H05K3/00 ,  H05K3/10 ,  H05K3/46

Abstract: A package structure includes a substrate, an insulator, a plurality of pads and a patterned circuit layer. The substrate includes a plurality of through holes. The insulator covers the substrate and is filled in the through hole. The conductive vias are located in the through holes and penetrate the insulator filled in the through holes. The pads are disposed on an upper surface and a lower surface of the insulator and electrically connected to the conductive vias. A bottom surface of each pad is lower than the top surface of the insulator. The patterned circuit layer is disposed on the top surface of the insulator and connected to the conductive vias and the pads. A bottom surface of the patterned circuit layer is lower than the top surface of the insulator.

公开(公告)号：US10090256B2

公开(公告)日：2018-10-02

申请号：US15364185

申请日：2016-11-29

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu ,  Wei-Jen Lai

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H05K1/03 ,  H05K3/18 ,  H05K3/40 ,  H05K1/11 ,  H05K3/00 ,  H05K3/10 ,  H05K3/46

Abstract: A semiconductor structure includes an insulating layer, a plurality of stepped conductive vias and a patterned circuit layer. The insulating layer includes a top surface and a bottom surface opposite to the top surface. The stepped conductive vias are disposed at the insulating layer to electrically connect the top surface and the bottom surface. Each of the stepped conductive vias includes a head portion and a neck portion connected to the head portion. The head portion is disposed on the top surface, and an upper surface of the head portion is coplanar with the top surface. A minimum diameter of the head portion is greater than a maximum diameter of the neck portion. The patterned circuit layer is disposed on the top surface and electrically connected to the stepped conductive vias.

公开(公告)号：US20170194241A1

公开(公告)日：2017-07-06

申请号：US15461499

申请日：2017-03-17

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu ,  Wei-Jen Lai

IPC: H01L23/498 ,  H01L23/29 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/186 ,  H01L2924/19105 ,  H05K1/0373 ,  H05K1/113 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674

Abstract: A package structure includes a substrate, an insulator, a plurality of pads and a patterned circuit layer. The substrate includes a plurality of through holes. The insulator covers the substrate and is filled in the through hole. The conductive vias are located in the through holes and penetrate the insulator filled in the through holes. The pads are disposed on an upper surface and a lower surface of the insulator and electrically connected to the conductive vias. A bottom surface of each pad is lower than the top surface of the insulator. The patterned circuit layer is disposed on the top surface of the insulator and connected to the conductive vias and the pads. A bottom surface of the patterned circuit layer is lower than the top surface of the insulator.

公开(公告)号：US20170077045A1

公开(公告)日：2017-03-16

申请号：US15364185

申请日：2016-11-29

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu ,  Wei-Jen Lai

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/35121 ,  H05K1/0373 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/09845 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00014

Abstract: A semiconductor structure includes an insulating layer, a plurality of stepped conductive vias and a patterned circuit layer. The insulating layer includes a top surface and a bottom surface opposite to the top surface. The stepped conductive vias are disposed at the insulating layer to electrically connect the top surface and the bottom surface. Each of the stepped conductive vias includes a head portion and a neck portion connected to the head portion. The head portion is disposed on the top surface, and an upper surface of the head portion is coplanar with the top surface. A minimum diameter of the head portion is greater than a maximum diameter of the neck portion. The patterned circuit layer is disposed on the top surface and electrically connected to the stepped conductive vias.

Abstract translation: 半导体结构包括绝缘层，多个阶梯形导电通孔和图案化电路层。 绝缘层包括顶表面和与顶表面相对的底表面。 阶梯状导电通孔设置在绝缘层处以电连接顶表面和底表面。 每个阶梯式导电通孔包括头部和连接到头部的颈部。 头部设置在顶表面上，头部的上表面与顶表面共面。 头部的最小直径大于颈部的最大直径。 图案化电路层设置在顶表面上并电连接到阶梯式导电通孔。

公开(公告)号：US09859193B2

公开(公告)日：2018-01-02

申请号：US15600793

申请日：2017-05-22

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu ,  Wei-Jen Lai

IPC: H01L23/495 ,  H01L23/60

CPC classification number: H01L23/49503 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/053 ,  H01L23/481 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49558 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/60 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/186 ,  H01L2924/19105 ,  H05K1/0373 ,  H05K1/113 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674

Abstract: A package structure including a substrate, a first lead frame, a first metal layer, at least one chip, a base and a second metal layer is provided. The base includes a plurality of openings. The first lead frame is embedded in the substrate and includes a plurality of first pads, where the openings expose the first pads. The first metal layer covers the exposed first pads. The chip is disposed on the substrate and electrically connected to the first metal layer and the first pads. The base covers the substrate with its bonding surface. The second metal layer covers a base surface of the base.