公开(公告)号：WO2010147846A3

公开(公告)日：2010-12-23

申请号：PCT/US2010/038202

申请日：2010-06-10

Applicant: KLA-TENCOR TECHNOLOGIES CORPORATION ,  STOKOWSKI, Stanley, E.

Inventor： STOKOWSKI, Stanley, E.

IPC: H01L21/027 ,  G03F1/08 ,  H01L21/66

Abstract: Provided are novel inspection methods and systems for inspecting unpatterned objects, such as extreme ultraviolet (EUV) mask blanks, for surface defects, including extremely small defects. Defects may include various phase objects, such as bumps and pits that are only about 1 nanometer in height, and small particles. Inspection is performed at wavelengths less than about 250 nanometers, such as a reconfigured deep UV inspection system. A partial coherence sigma is set to between about 0.15 and 0.5. Phase defects can be found by using one or more defocused inspection passes, for example at one positive depth of focus (DOF) and one negative DOF. In certain embodiments, DOF is between about -1 to -3 and/or +1 to +3. The results of multiple inspection passes can be combined to differentiate defect types. Inspection methods may involve applying matched filters, thresholds, and/or correction factors in order to improve a signal to noise ratio.

公开(公告)号：WO2009061579A1

公开(公告)日：2009-05-14

申请号：PCT/US2008/079332

申请日：2008-10-09

Applicant: KLA-TENCOR TECHNOLOGIES CORPORATION ,  GRELLA, Luca ,  BARANOV, Leonid ,  GOTKIS, Yehiel

Inventor： GRELLA, Luca ,  BARANOV, Leonid ,  GOTKIS, Yehiel

IPC: H01L21/027

CPC classification number: H01J37/3174 ,  B82Y10/00 ,  B82Y40/00 ,  H01J2237/0435 ,  H01J2237/0453

Abstract: One embodiment relates to a dynamic pattern generator (112) for reflection electron beam lithography which includes conductive pixel pads (902), an insulative border (906) surrounding each conductive pixel pad so as to electrically isolate the conductive pixel pads from each other, and conductive elements (908) coupled to the conductive pixel pads for controllably applying voltages to the conductive pixel pads. The conductive pixel pads are advantageously cup shaped with a bottom portion, a sidewall portion, and an open cavity (904). Another embodiment relates to a pattern generating apparatus which includes a well structure with sidewalls and a cavity configured above each conductive pixel pad (1210). The sidewalls may include alternating layers of conductive (1212, 1214, 1216) and insulative (1202, 1204, 1206) materials. Other embodiments, aspects and feature are also disclosed.

Abstract translation: 一个实施例涉及用于反射电子束光刻的动态图案发生器（112），其包括导电像素焊盘（902），围绕每个导电像素焊盘的绝缘边界（906），以将导电像素焊盘彼此电隔离;以及 耦合到导电像素焊盘的导电元件（908），用于可控地向导电像素焊盘施加电压。 导电像素焊盘有利地为杯形，其具有底部，侧壁部分和开放空腔（904）。 另一实施例涉及一种图案生成装置，其包括具有侧壁的阱结构和在每个导电像素焊盘（1210）上方配置的空腔。 侧壁可以包括交替的导电层（1212,1214,1216）和绝缘（1202,1204,1206）材料。 还公开了其它实施例，方面和特征。

公开(公告)号：WO2008153770A2

公开(公告)日：2008-12-18

申请号：PCT/US2008/006654

申请日：2008-05-23

Applicant: KLA-TENCOR TECHNOLOGIES CORPORATION ,  ARMSTRONG, J., Joseph ,  CHUANG, Yung-Ho ,  BROWN, David, Lee

Inventor： ARMSTRONG, J., Joseph ,  CHUANG, Yung-Ho ,  BROWN, David, Lee

IPC: H01L21/66

CPC classification number: G01N21/9501 ,  G01N21/95623 ,  G01N2021/8822 ,  G01N2021/95676

Abstract: An improved inspection system using back-side illuminated linear sensing for propagating charge through a sensor is provided. Focusing optics may be used with a back side illuminated linear sensor to inspect specimens, the back side illuminated linear sensor operating to advance an accumulated charge from one side of each pixel to the other side. The design comprises controlling voltage profiles across pixel gates from one side to the other side in order to advance charge between to a charge accumulation region. Controlling voltage profiles comprises attaching a continuous polysilicon gate across each pixel within a back side illuminated linear sensor array. Polysilicon gates and voltages applied thereto enable efficient electron advancement using a controlled voltage profile.

Abstract translation: 提供了一种使用背面照明线性检测的改进的检测系统，用于通过传感器传播电荷。 聚焦光学元件可以与背面照明的线性传感器一起使用以检查样品，背面照射的线性传感器操作以将累积的电荷从每个像素的一侧推进到另一侧。 该设计包括控制从一侧到另一侧的像素栅极之间的电压分布，以便在电荷累积区域之间推进电荷。 控制电压分布包括在背侧照明线性传感器阵列内的每个像素上连接连续的多晶硅栅极。 多晶硅栅极和施加于其上的电压使得能够使用受控电压分布进行有效的电子前进。

公开(公告)号：WO2008086527A2

公开(公告)日：2008-07-17

申请号：PCT/US2008/050913

申请日：2008-01-11

Applicant: KLA-TENCOR TECHNOLOGIES CORPORATION ,  CARROLL, Allen M.

Inventor： CARROLL, Allen M.

IPC: H01J37/317 ,  H01J37/073

CPC classification number: H01J1/34 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/073 ,  H01J37/3174 ,  H01J2237/06333 ,  H01J2237/31779

Abstract: Embodiments of the invention include an electron beam lithography device using a dynamically controllable photocathode capable of producing a patterned electron beam. One such implementation includes a dynamic pattern generator configurable to produce an electron beam having a desired image pattern impressed thereon. Such an electron beam pattern being enabled by selectively activating programmable photoemissive elements of the pattern generator. The apparatus further including an illumination source arranged to direct a light beam onto the dynamic pattern generator to produce the electron beam having the desired pattern. The electron beam being directed through associated electron optics configured to receive the electron beam from the dynamic pattern generator and direct the electron beam onto a target substrate mounted on a stage.

Abstract translation: 本发明的实施例包括使用能够产生图案化电子束的动态可控光电阴极的电子束光刻装置。 一种这样的实现包括动态图案发生器，其被配置为产生具有所加载的所需图像图案的电子束。 这种电子束图案通过选择性地激活图案发生器的可编程发光元件来实现。 该装置还包括照明源，其被布置成将光束引导到动态图案发生器上以产生具有期望图案的电子束。 电子束通过相关联的电子光学器件被配置成从动态图案发生器接收电子束并将电子束引导到安装在载物台上的目标基底上。

公开(公告)号：WO2008086494A2

公开(公告)日：2008-07-17

申请号：PCT/US2008/050798

申请日：2008-01-10

Applicant: KLA-TENCOR TECHNOLOGIES CORPORATION ,  XIONG, Yalin ,  SHI, Rui-fang

Inventor： XIONG, Yalin ,  SHI, Rui-fang

CPC classification number: G03F1/84 ,  G01N21/95607 ,  G03F7/7065 ,  G03F7/70666

Abstract: A method and tool for generating reconstructed images that model the high NA effects of a lithography tool used to image patterns produced by a mask. Comparison of the reconstructed images with reference images characterize the mask. The method involves providing a mask reticle for inspection. Generating matrix values associated with a high NA corrective filter matrix that characterizes a high NA lithography system used to print from the mask. Illuminating the mask to produce a patterned illumination beam that is filtered with filters associated with the high NA corrective filter matrix elements to obtain a plurality of filtered beams that include raw image data that is processed to obtain a reconstructed image that is further processed and compared with reference images to obtain mask characterization information.

Abstract translation: 用于生成重建图像的方法和工具，所述重建图像模拟用于成像由掩模产生的图案的光刻工具的高NA效应。 重建图像与参考图像的比较表征掩模。 该方法涉及提供用于检查的掩模光罩。 生成与高NA校正滤波器矩阵相关联的矩阵值，其表征用于从掩模打印的高NA光刻系统。 照亮掩模以产生图案化照明光束，其用与高NA校正滤波器矩阵元素相关联的滤波器滤波以获得包括原始图像数据的多个滤波的光束，所述原始图像数据被处理以获得重建图像，所述重构图像被进一步处理并与 参考图像以获得掩模表征信息。

公开(公告)号：WO2008036827A2

公开(公告)日：2008-03-27

申请号：PCT/US2007/079053

申请日：2007-09-20

Applicant: KLA-TENCOR TECHNOLOGIES CORPORATION ,  ADEL, Michael ,  CHANG, Ellis

Inventor： ADEL, Michael ,  CHANG, Ellis

IPC: G06F17/50

CPC classification number: G03F7/70633 ,  G03F7/70533

Abstract: The invention is a method for generating a design rule map having a spatially varying overlay error budget. Additionally, the spatially varying overlay error budget can be employed to determine if wafers are fabricated in compliance with specifications. In one approach a design data file that contains fabrication process information and reticle information is processed using design rules to obtain a design map with a spatially varying overlay error budget that defines a localized tolerance to overlay errors for different spatial locations on the design map. This spatially varying overlay error budget can be used to disposition wafers. For example, overlay information obtained from measured metrology targets on a fabricated wafer are compared with the spatially varying overlay error budget to determine if the wafer overlay satisfies the required specification.

Abstract translation: 本发明是一种用于生成具有空间变化的重叠误差预算的设计规则图的方法。 此外，可以采用空间上可变的重叠误差预算来确定晶片是否符合规格制造。 在一种方法中，使用设计规则处理包含制造过程信息和掩模版信息的设计数据文件，以获得具有空间上变化的重叠误差预算的设计图，该设计图定义了设计图上不同空间位置的重叠误差的局部容差。 这种空间上可变的重叠误差预算可用于配置晶片。 例如，将从制造的晶片上的测量的测量目标获得的覆盖信息与空间上变化的重叠误差预算进行比较，以确定晶片覆盖是否满足要求的规范。

公开(公告)号：WO2008027543A2

公开(公告)日：2008-03-06

申请号：PCT/US2007/019188

申请日：2007-08-29

Applicant: KLA-TENCOR TECHNOLOGIES CORPORATION ,  ADLER, David L

Inventor： ADLER, David L

IPC: G01N23/225

CPC classification number: G01N23/225 ,  H01J37/256 ,  H01J37/28 ,  H01J2237/2803

Abstract: One embodiment relates to an apparatus using electrons for inspection or metrology of a semiconductor substrate. The apparatus includes an electron source (301), electron lenses (302), scan deflectors (304), an objective electron lens (305), a collection electron lens (310), a pin-hole filter (312), de-scan deflectors (311), and a detector (313). The collection electron lens (310) is configured to focus the secondary electrons so as to form a secondary electron beam (309) which is focused at a conjugate focal plane, and the pin-hole filter (312) is positioned at the conjugate focal plane. The de-scan deflectors (311) are configured to controllably deflect the secondary electrons so as to counteract an influence of the scan deflectors (304) such that a center portion of the secondary electron beam passes through the filter and a remainder portion of the secondary electron beam is filtered out by the filter. Other embodiments and features are also disclosed.

Abstract translation: 一个实施例涉及使用电子来检查或计量半导体衬底的设备。 该装置包括电子源（301），电子透镜（302），扫描偏转器（304），物镜电子透镜（305），收集电子透镜（310），针孔滤波器（312），去扫描 偏转器（311）和检测器（313）。 集光电子透镜（310）被配置为聚焦二次电子以形成聚焦在共轭焦平面处的二次电子束（309），并且针孔滤光器（312）被定位在共轭焦平面 。 去扫描偏转器（311）被配置为可控制地偏转二次电子，从而抵消扫描偏转器（304）的影响，使得二次电子束的中心部分穿过滤波器，而次级电子束的剩余部分 电子束被滤波器滤除。 其他实施例和特征也被公开。

公开(公告)号：WO2007143056A3

公开(公告)日：2007-12-13

申请号：PCT/US2007/012875

申请日：2007-05-31

Applicant: KLA-TENCOR TECHNOLOGIES CORPORATION ,  KANDEL, Daniel ,  LEVINSKI, Vladimir ,  ADEL, Michael, E. ,  SELIGSON, Joel, L.

Inventor： KANDEL, Daniel ,  LEVINSKI, Vladimir ,  ADEL, Michael, E. ,  SELIGSON, Joel, L.

IPC: G01N21/00 ,  G01B11/30

Abstract: Disclosed are apparatus and methods for measuring a characteristic, such as overlay, of a semiconductor target. In general, order-selected imaging and/or illumination is performed while collecting an image from a target using a metrology system. In one implementation, tunable spatial modulation is provided only in the imaging path of the system. In other implementations, tunable spatial modulation is provided in both the illumination and imaging paths of the system. In a specific implementation, tunable spatial modulation is used to image side-by-side gratings with diffraction orders ±n. The side-by-side gratings may be in different layers or the same layer of a semiconductor wafer. The overlay between the structures is typically found by measuring the distance between centers symmetry of the gratings. In this embodiment, only orders ±n for a given choice of n (where n is an integer and not equal to zero) are selected, and the gratings are only imaged with these diffraction orders.

公开(公告)号：WO2007112300A2

公开(公告)日：2007-10-04

申请号：PCT/US2007/064769

申请日：2007-03-23

Applicant: KLA-TENCOR TECHNOLOGIES CORPORATION ,  WACK, Dan ,  WANG, Haiming ,  GROSS, Kenneth P.

Inventor： WACK, Dan ,  WANG, Haiming ,  GROSS, Kenneth P.

IPC: G01B11/14 ,  G01N21/55

CPC classification number: G01B11/24 ,  G01N21/211 ,  G01N21/47 ,  G01N21/956 ,  G01N2021/213 ,  G01N2021/217 ,  G01N2021/4707 ,  G01N2021/4711 ,  G01N2021/4792

Abstract: Systems and methods for measuring one or more characteristics of patterned features on a specimen are provided. One system includes an optical subsystem configured to acquire measurements of light scattered from the patterned features on the specimen at multiple angles of incidence, multiple azimuthal angles, and multiple wavelengths simultaneously. The system also includes a processor configured to determine the one or more characteristics of the patterned features from the measurements. One method includes acquiring measurements of light scattered from the patterned features on the specimen at multiple angles of incidence, multiple azimuthal angles, and multiple wavelengths simultaneously. The method also includes determining the one or more characteristics of the patterned features from the measurements.

Abstract translation: 提供了用于测量样本上的图案特征的一个或多个特征的系统和方法。 一个系统包括光学子系统，被配置为从多个入射角，多个方位角和多个波长同时获取从样本上的图案化特征散射的光的测量。 该系统还包括配置成从测量中确定图案化特征的一个或多个特性的处理器。 一种方法包括以多个入射角，多个方位角和多个波长同时从样本上的图案化特征散射的光的测量。 该方法还包括从测量中确定图案化特征的一个或多个特性。

公开(公告)号：WO2007100933A2

公开(公告)日：2007-09-07

申请号：PCT/US2007/060503

申请日：2007-01-12

Applicant: KLA TENCOR TECHNOLOGIES CORPORATION ,  NASSER-GHODSI, Mehran ,  GOTKIS, Yehiel ,  LOPATIN, Sergey ,  PICKARD, Garrett ,  GARCIA, Rudy F. ,  YU, Ming Lun ,  KRZECZOWSKI, Kenneth ,  LENT, Matthew ,  HUANG, Chris ,  MACDONALD, Niles K. ,  BOROWICZ, Stanislaw Marek ,  CHUANG, Tzu-chin

Inventor： NASSER-GHODSI, Mehran ,  GOTKIS, Yehiel ,  LOPATIN, Sergey ,  PICKARD, Garrett ,  GARCIA, Rudy F. ,  YU, Ming Lun ,  KRZECZOWSKI, Kenneth ,  LENT, Matthew ,  HUANG, Chris ,  MACDONALD, Niles K. ,  BOROWICZ, Stanislaw Marek ,  CHUANG, Tzu-chin

IPC: C23F1/00 ,  A61N5/00 ,  G21G5/00

CPC classification number: G03F7/2043 ,  H01J2237/31732 ,  H01J2237/3174 ,  H01J2237/31744 ,  H01L21/02057 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/32136

Abstract: Etch selectivity enhancement during electron beam activated chemical etch (EBACE), methods and apparatus for evaluating the quality of structures on an integrated circuit wafer using EBACE, a method for modifying a surface of a substrate (or a portion there of), methods and apparatus for imaging a structure and an associated processor-readable medium are disclosed. A target or portion thereof may be exposed to a gas composition of a type that etches the target when the gas composition and/or target are exposed to an electron beam. By directing an electron beam toward the target in the vicinity of the gas composition, an interaction between the electron beam and the gas composition etches a portion of the target exposed to both the gas composition and the electron beam.

Abstract translation: 电子束激活化学蚀刻（EBACE）中的蚀刻选择性增强，用于使用EBACE评估集成电路晶片上的结构质量的方法和装置，用于改变衬底（或其部分）的表面的方法，方法和装置 用于对结构进行成像和相关联的处理器可读介质。 当气体组合物和/或靶暴露于电子束时，靶或其部分可暴露于蚀刻靶的类型的气体组合物。 通过在气体组合物附近引导电子束朝向靶，电子束和气体组成之间的相互作用会蚀刻暴露于气体组成和电子束两者的靶的一部分。