公开(公告)号：EP1729338B1

公开(公告)日：2016-07-06

申请号：EP06010091.4

申请日：2006-05-16

Applicant: Nanya Technology Corporation

Inventor： Lee, Pei-Ing

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10891

公开(公告)号：EP1732125B1

公开(公告)日：2013-04-24

申请号：EP06011004.6

申请日：2006-05-29

Applicant: Nanya Technology Corporation

Inventor： Lee, Pei-Ing

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/10888 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/7834

公开(公告)号：EP2490221A1

公开(公告)日：2012-08-22

申请号：EP11154812.9

申请日：2011-02-17

Applicant: Nanya Technology Corporation

Inventor： Ting, Tah-Kang Joseph

IPC: G11C11/405 ,  G11C7/02 ,  G11C11/4097 ,  G11C7/18

CPC classification number: G11C11/405 ,  G11C7/02 ,  G11C7/18 ,  G11C11/4097

Abstract: This invention relates to a memory cell (100) having a first switch device (105), a second switch device (107) and a capacitor (109). The first switch device (105) has: a control terminal for receiving a first control signal (CS 1 ) transmitted by a first select line (102), wherein the first switch device is turned on or turned off according to the first control signal (CS 1 ); a first terminal, coupled to a data line (101); and a second terminal. The second switch device (107) has: a first terminal, coupled to the second terminal of the first switch device (105); a control terminal for receiving a second control signal (CS2) transmitted by a second select line (103), wherein the second switch device (107) is turned on or turned off according to the second control signal (CS2); and a second terminal. The capacitor (109) has a first terminal coupled to the second terminal of the second switch device (107) and a second terminal coupled to a predetermined voltage level. The data is read from the capacitor (109) or written to the capacitor (109) via the data line (101).

Abstract translation: 本发明涉及具有第一开关装置（105），第二开关装置（107）和电容器（109）的存储单元（100）。 第一开关装置（105）具有：控制端子，用于接收由第一选择线（102）发送的第一控制信号（CS1），其中，第一开关装置根据第一控制信号而导通或截止 CS 1）; 耦合到数据线（101）的第一终端; 和第二终端。 第二开关装置（107）具有：耦合到第一开关装置（105）的第二端子的第一端子; 控制终端，用于接收由第二选择线（103）发送的第二控制信号（CS2），其中所述第二开关装置（107）根据所述第二控制信号（CS2）导通或关断; 和第二终端。 电容器（109）具有耦合到第二开关装置（107）的第二端子的第一端子和耦合到预定电压电平的第二端子。 数据从电容器（109）读取或通过数据线（101）写入电容器（109）。

公开(公告)号：EP2372772A3

公开(公告)日：2012-04-11

申请号：EP10006089.6

申请日：2010-06-11

Applicant: Nanya Technology Corporation

Inventor： Wu, Tieh-Chiang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7851 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10894 ,  H01L29/66795

Abstract: A dual channel transistor (50) includes a semiconductor island (22) isolated by a first shallow trench isolation (STI) (12) extending along a first direction and a second STI (20) extending along a second direction, wherein the first direction intersects the second direction. The dual channel transistor (50) further includes a gate trench (26) recessed into the semiconductor island (26) and extending along the second direction. A gate (30) is located in the gate trench (26). A first U-shaped channel region (60) is formed in the semiconductor island (22). A second U-shaped channel region (62) is formed in the semiconductor island (22), wherein the second U-shaped channel region (62) is segregate from the first U-shaped channel region (60) by the gate (30). During operation, the gate (30) controls two U-shaped channel regions (60, 62) simultaneously.

公开(公告)号：EP2393118A1

公开(公告)日：2011-12-07

申请号：EP10005773.6

申请日：2010-06-02

Applicant: Nanya Technology Corporation

Inventor： Renn, Shing-Hwa

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7853 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66818

Abstract: A single-gate FinFET structure includes an active fin structure having two enlarged head portions and a tapered neck portion that connects the enlarged head portions with an underlying ultra-thin body. Two source/drain regions are doped in the two enlarged head portions respectively. An insulation region is interposed between the two source/drain regions. A trench isolation structure is disposed at one side of the tuning fork-shaped fin structure. A single-sided sidewall gate electrode is disposed on a vertical sidewall of the active fin structure opposite to the trench isolation structure.

Abstract translation: 单栅极FinFET结构包括具有两个扩大头部的有源鳍结构和将扩大的头部与下面的超薄体连接的锥形颈部。 在两个扩大头部分别分别掺杂两个源极/漏极区域。 在两个源极/漏极区域之间插入绝缘区域。 沟槽隔离结构设置在音叉形翅片结构的一侧。 单面侧壁栅电极设置在与沟槽隔离结构相对的有源鳍结构的垂直侧壁上。

公开(公告)号：EP2372772A2

公开(公告)日：2011-10-05

申请号：EP10006089.6

申请日：2010-06-11

Applicant: Nanya Technology Corporation

Inventor： Wu, Tieh-Chiang

IPC: H01L29/78 ,  H01L21/336

Abstract: A dual channel transistor (50) includes a semiconductor island (22) isolated by a first shallow trench isolation (STI) (12) extending along a first direction and a second STI (20) extending along a second direction, wherein the first direction intersects the second direction. The dual channel transistor (50) further includes a gate trench (26) recessed into the semiconductor island (26) and extending along the second direction. A gate (30) is located in the gate trench (26). A first U-shaped channel region (60) is formed in the semiconductor island (22). A second U-shaped channel region (62) is formed in the semiconductor island (22), wherein the second U-shaped channel region (62) is segregate from the first U-shaped channel region (60) by the gate (30). During operation, the gate (30) controls two U-shaped channel regions (60, 62) simultaneously.

Abstract translation: 双通道晶体管（50）包括通过沿着第一方向延伸的第一浅沟槽隔离（STI）（12）和沿第二方向延伸的第二STI（20）隔离的半导体岛（22），其中第一方向与 第二个方向。 双通道晶体管（50）还包括凹入半导体岛（26）并沿着第二方向延伸的栅极沟槽（26）。 栅极（30）位于栅极沟槽（26）中。 第一U形沟道区（60）形成在半导体岛（22）中。 第二U形沟道区域（62）形成在半岛岛（22）中，其中第二U形沟道区域（62）通过栅极（30）与第一U形沟道区域（60）隔离， 。 在操作期间，门（30）同时控制两个U形通道区域（60,62）。

公开(公告)号：EP1732125A3

公开(公告)日：2009-04-15

申请号：EP06011004.6

申请日：2006-05-29

Applicant: Nanya Technology Corporation

Inventor： Lee, Pei-Ing

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10888 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/7834

Abstract: A method for forming a semiconductor memory device with buried contacts. A substrate (100) is provided, wherein the substrate has recessed gates (118) and deep trench capacitor devices (102) therein. Protrusions (120) of the recessed gates and upper portions (104) of the deep trench capacitor devices are revealed. Spacers (124) are formed on sidewalls of the upper portions and the protrusions. Buried portions of conductive material (130) are formed in spaces between the spacers. The substrate, the spacers and the buried portions to form parallel shallow trenches are patterned to form parallel shallow trenches (132) for defining active regions. A layer of dielectric material is formed in the shallow trenches, wherein some of the buried portions serve as buried contacts.

公开(公告)号：EP1732124A3

公开(公告)日：2009-04-15

申请号：EP06010424.7

申请日：2006-05-19

Applicant: Nanya Technology Corporation

Inventor： Lee, Pei-Ing

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10888 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/7834

Abstract: A method for forming a semiconductor device. A substrate (100) is provided, wherein the substrate has recessed gates (118) and deep trench capacitor devices (102) therein. Protrusions (120) of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers (124) are formed on sidewalls of the upper portions (104) and the protrusions. Buried portions of conductive material (134a,b) are formed in spaces between the spacers. The substrate, the spacers and the buried portions are patterned to form parallel shallow trenches (132) for defining active regions. A layer of dielectric material is formed in the shallow trenches, wherein some of the buried portions (134a) serve as buried bit line contacts. Word lines (140) are formed across the recessed gates (120), wherein at least one of the word lines comprises portions overlapping the recessed gates. At least one of the overlapped portions has a narrower width than at least one of the recessed gates.

公开(公告)号：EP1953842A2

公开(公告)日：2008-08-06

申请号：EP07024442.1

申请日：2007-12-17

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE ,  Powerchip Semiconductor Corp. ,  Nanya Technology Corporation ,  ProMOS Technologies, Inc. ,  WINBOND ELECTRONICS CORPORATION

Inventor： Hsu, Hong-Hui

IPC: H01L45/00

CPC classification number: H01L45/1675 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148

Abstract: A phase change memory device and fabrication method thereof is provided. The phase change memory device includes a substrate (300). A metal plug (304) is disposed on the substrate and a phase change material film (306a) is disposed on the metal plug, wherein the metal plug is electrically connected to the phase change material film. A heating electrode (312), preferably ring-shaped, is disposed on the phase change material film, wherein the heating electrode is electrically connected to the phase change material film. A conductive layer (316) is disposed on the heating electrode.

Abstract translation: 提供了一种相变存储器件及其制造方法。 相变存储器件包括衬底（300）。 金属插头（304）设置在基板上，相变材料膜（306a）设置在金属插塞上，其中金属插塞与相变材料膜电连接。 在相变材料膜上设置优选环状的加热电极（312），其中，加热电极与相变材料膜电连接。 导电层（316）设置在加热电极上。

公开(公告)号：US20250166898A1

公开(公告)日：2025-05-22

申请号：US18515291

申请日：2023-11-21

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chih-Chun HSIAO ,  Ji-Feng LIU

IPC: H01G4/008 ,  H01G4/12 ,  H01G4/38

Abstract: A method of manufacturing a capacitor includes forming a bottom electrode layer; forming an insulator on the bottom electrode layer; crystallizing the insulator; and forming a top electrode layer on the crystallized insulator. As such, the leakage problem due to thinner top electrode layer and smaller critical dimension of the capacitor can be reduced. In addition, possibility for the capacitors to collapse is reduced, and the electrical performance of the capacitor won't be affected by the collapse problem.