公开(公告)号：JP2005064498A

公开(公告)日：2005-03-10

申请号：JP2004227056

申请日：2004-08-03

Applicant: Phoenix Precision Technology Corp ,  全懋精密科技股▲分▼有限公司

Inventor： HSU SHIH-PING ,  TSAI KUN-CHEN

IPC: H01L21/60 ,  H01L21/48 ,  H01L23/498 ,  H05K3/10 ,  H05K3/24 ,  H05K3/28 ,  H05K3/42

CPC classification number: H01L24/02 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K1/113 ,  H05K3/108 ,  H05K3/243 ,  H05K3/28 ,  H05K3/423 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/0574 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor packaging board structure, which has a metal protective layer for an electrical connection pad, and to provide a manufacturing method for the board structure.
SOLUTION: According to the board structure and the manufacturing method, a plurality of blind holes are made on an insulating layer 30 to provide the insulating layer 30 whose undersurface is coated with an inner layer circuit 30a that is exposed. A conductive film is formed on the surface of the insulating layer 30 and of the blind holes, and the conductive film is covered with a first resist pattern having a number of openings, which is then subjected to an electroplating process to form a pattern circuit layer including the electrical connection pad 330. The pattern circuit layer, other than the electrical connection pad, is coated with a second resist layer so that the electrical connection pad is exposed from the second resist layer. Then a barrier metal layer 35 is formed on the exposed electrical connection pad 330 via an electroplating process, and the layer 35 is covered with a solder mask layer 36, then is exposed by another step.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 解决的问题：提供一种半导体封装板结构，其具有用于电连接焊盘的金属保护层，并且提供用于板结构的制造方法。 解决方案：根据板结构和制造方法，在绝缘层30上形成多个盲孔，以提供其下表面涂覆有暴露的内层电路30a的绝缘层30。 在绝缘层30和盲孔的表面上形成导电膜，并且用具有多个开口的第一抗蚀剂图案覆盖导电膜，然后进行电镀处理以形成图案电路层 包括电连接焊盘330.除了电连接焊盘之外的图案电路层涂覆有第二抗蚀剂层，使得电连接焊盘从第二抗蚀剂层露出。 然后通过电镀工艺在暴露的电连接焊盘330上形成阻挡金属层35，并且用焊料掩模层36覆盖层35，然后通过另一步骤暴露。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：US20030122256A1

公开(公告)日：2003-07-03

申请号：US10364431

申请日：2003-02-10

Applicant: Phoenix Precision Technology Corp.

Inventor： Shih-Ping Hsu ,  Chiang-Du Chen ,  Yen-Hung Liu

IPC: H01L023/48

CPC classification number: H01L23/49811 ,  H01L21/4846 ,  H01L2924/0002 ,  H05K3/243 ,  H05K2203/0542 ,  H05K2203/0577 ,  H05K2203/1476 ,  H01L2924/00

Abstract: The present invention discloses a substrate within a Ni/Au structure electroplated on electrical contact pads and a method for fabricating the same. The method comprises: providing a substrate with a circuit layout pattern and forming a conducting film on the surface of the substrate; depositing a first photoresist layer within an opening on said electrical conducting film surface to expose a portion of said circuit layout pattern to be electrical contact pads; removing the exposed conducting film uncovered by the first photoresist layer; depositing a second photoresist layer, covering the conducting film exposed in the openings of the first photoresist layer; electroplating Ni/Au covering the surface of the electrical contact pads; removing the first and second photoresists, and the conducting film covered by the photoresists; depositing solder mask on the substrate within an opening to expose said electrical contact pads. It improves the electrical coupling between gold wires and the electrical contact pads of the substrate, prevents the electrical contact pads from oxidation, and insurances the electrical interconnection performance.

公开(公告)号：US20020189853A1

公开(公告)日：2002-12-19

申请号：US09957372

申请日：2001-09-20

Applicant: Phoenix Precision Technology Corp.

Inventor： Shih-Ping Hsu

IPC: H05K007/20

CPC classification number: H01L23/49816 ,  H01L23/3677 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/32188 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: BGA substrate with direct heat dissipating structure The present invention discloses a structure of BGA substrate with direct heat-dissipating structure, said structure comprising: a heat spreader, no less than one insulating resin layer, an upper circuit layer, a lower circuit layer, and a plurality of electrically-conducting plugs. The heat spreader comprises a body part, a loading part, and a junction part. The loading part is the upper region of heat spreader. The junction part is the lower region of the heat spreader. The periphery of said junction part extends outward for forming a protruding edge. The body part is embedded into the central region of the substrate. The upper circuit layer is formed on the surface of said resin layer. The lower circuit layer is formed on lower surface of said resin layer and comprises a plurality of solder pads. The upper and lower circuit layers are conducted by electrically conductive plugs. The heat generated from chip is dissipated by heat spreader instead of heat-conducting plugs in traditional art. The cross sectional area of heat spreader is larger than the heat-conducting plug, which enhances the performance of heat dissipation.

Abstract translation: 具有直接散热结构的BGA基板本发明公开了一种具有直接散热结构的BGA基板的结构，所述结构包括：散热器，不少于一个绝缘树脂层，上电路层，下电路层和 多个导电插头。 散热器包括主体部分，装载部分和接合部分。 装载部分是散热器的上部区域。 接头部分是散热器的下部区域。 所述接合部分的周边向外延伸以形成突出边缘。 主体部分嵌入基板的中心区域。 上层电路层形成在树脂层的表面上。 下电路层形成在所述树脂层的下表面上并且包括多个焊盘。 上下电路层由导电插头导电。 由散热器代替传统技术中的导热塞，从芯片产生的热量消散。 散热器的横截面积大于导热塞，从而提高散热性能。